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FeaTures
Full Featured Li-Ion/Polymer Charger/PowerPathTM Controller with Instant-On Operation n Triple Adjustable High Efficiency Step-Down Switching Regulators (800mA, 500mA, 500mA IOUT) n I2C Adjustable SW Slew Rates for EMI Reduction n High Temperature Battery Voltage Reduction Improves Safety and Reliability n OvervoltageProtectionControllerforUSB(V BUS)/Wall InputsProvideProtectionto30V n 1.5AMaximumChargeCurrentwithThermalLimiting n BatteryFloatVoltage:4.2V n PushbuttonON/OFFControlwithSystemReset n Dual150mACurrentLimitedLDOs n Start-UpTimingCompatiblewithSiRFAtlasIV Processor n Small4mmx7mm44-PinQFNPackage
n
LTC3677-3 Highly Integrated Portable Product PMIC DescripTion
TheLTC(R)3677-3isahighlyintegratedpowermanagement IC for single-cell Li-Ion/Polymer battery applications. It includes a PowerPath manager with automatic load prioritization,abatterycharger,anidealdiode,inputovervoltageprotectionandnumerousotherinternalprotection features.TheLTC3677-3isdesignedtoaccuratelycharge fromcurrentlimitedsuppliessuchasUSBbyautomatically reducingchargecurrentsuchthatthesumoftheload currentandthechargecurrentdoesnotexceedtheprogrammedinputcurrentlimit(100mAor500mAmodes). TheLTC3677-3reducesthebatteryvoltageatelevated temperaturestoimprovesafetyandreliability.Thethree step-downswitchingregulatorsandtwoLDOsprovide awiderangeofavailablesupplies.TheLTC3677-3also includesapushbuttoninputtocontrolpowersequencing andsystemreset.TheLTC3677-3haspushbuttontimingandsequencingdesignedtosupporttheSiRFAtlas IVprocessor.TheLTC3677-3isavailableinalowprofile 4mmx7mmx0.75mm44-pinQFNpackage.
L,LT,LTC,LTM,LinearTechnology,PowerPath,BurstModeandtheLinearlogoareregistered trademarksandBat-TrackandHotSwaparetrademarksofLinearTechnologyCorporation. Allothertrademarksarethepropertyoftheirrespectiveowners.ProtectedbyU.S.Patents, including6522118,6700364,7511390,5481178,6580258.Otherpatentspending.
applicaTions
PNDs,DMB/DVB-H,Digital/SatelliteRadio, MediaPlayers n PortableIndustrial/MedicalProducts n OtherUSB-BasedHandheldProducts
n
Typical applicaTion
5V ADAPTER USB OVERVOLTAGE PROTECTION CHARGE 2
High Temperature BAT Discharge
OPTIONAL 100mA/500mA 1000mA VOUT 0V SINGLE-CELL Li-Ion 0.8V to 3.6V/150mA 0.8V to 3.6V/150mA 0.8V to 3.6V/800mA 0.8V to 3.6V/500mA 0.8V to 3.6V/500mA
36773 TA01a
200
VNTC < VTOO_HOT 180 VBUS = 0V 160 140 IBAT (mA)
CC/CV CHARGER LTC3677-3 I2C PORT NTC
+
120 100 80 60 40 20 0 3.8 3.9 4.0 VBAT (V) 4.1 4.2
36773 TA01b
DUAL LDO REGULATORS TRIPLE HIGH EFFICIENCY STEP-DOWN SWITCHING REGULATORS
PB
PUSHBUTTON CONTROL
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LTC3677-3
Features ............................................................................................................................ 1 Applications ....................................................................................................................... 1 Typical Application ............................................................................................................... 1 Description......................................................................................................................... 1 Absolute Maximum Ratings ..................................................................................................... 3 Order Information ................................................................................................................. 3 Pin Configuration ................................................................................................................. 3 Electrical Characteristics ........................................................................................................ 4 Typical Performance Characteristics .........................................................................................10 Pin Functions .....................................................................................................................15 Block Diagram....................................................................................................................18 Operation..........................................................................................................................19 PowerPathOPERATION........................................................................................................................................ 19 LowDropoutLinearRegulatorOperation............................................................................................................. 27 Step-DownSwitchingRegulatorOperation.......................................................................................................... 28 . 2COperation........................................................................................................................................................ 32 I PushbuttonInterfaceOperation............................................................................................................................ 36 LayoutandThermalConsiderations..................................................................................................................... 40 Typical Application ..............................................................................................................42 Package Description ............................................................................................................43 Typical Application ..............................................................................................................44 Related Parts .....................................................................................................................44
Table oF conTenTs
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LTC3677-3 absoluTe MaxiMuM raTings
(Notes 1, 2, 3)
pin conFiguraTion
TOP VIEW 44 CHRG 43 CLPROG 42 EXTPWR 41 ACPR 40 VBUS 39 VOUT 38 BAT ILIM0 1 ILIM1 2 NC 3 WALL 4 SW3 5 VIN3 6 FB3 7 OVSENS 8 NC 9 DVCC 10 SDA 11 SCL 12 OVGATE 13 PWR_ON 14 ON 15 45 GND 37 IDGATE 36 PROG 35 NTC 34 NTCBIAS 33 SW1 32 VIN12 31 SW2 30 VINLD02 29 LDO2 28 LDO1 27 VINLDO1 26 FB1 25 FB2 24 LDO2_FB 23 LDO1_FB UFF PACKAGE 44-LEAD (7mm 4mm) PLASTIC QFN TJMAX=110C,JA=45C/W EXPOSEDPAD(PIN45)ISGND,MUSTBESOLDEREDTOPCB PBSTAT 16 EN3 17 NC 18 NC 19 NC 20 PGOOD 21 NC 22
VBUS,VOUT,VIN12,VIN3,VINLDO1,VINLDO2,WALL t<1msandDutyCycle<1% .................. -0.3Vto7V . SteadyState............................................ -0.3Vto6V CHRG,BAT,PWR_ON,EXTPWR,PBSTAT,PGOOD, FB1,FB2,FB3,LDO1,LDO1_FB,LDO2, LDO2_FB,DVCC,SCL,SDA,EN3................. -0.3Vto6V NTC,PROG,CLPROG,ON,ILIM0,ILIM1 (Note4).......................................... -0.3VtoVCC+0.3V . IVBUS,IVOUT,IBAT,Continuous(Note16).....................2A ISW3,Continuous(Note16)................................ 850mA . ISW2,ISW1,Continuous(Note16)....................... 600mA . ILDO1,ILDO2,Continuous(Note16)..................... 200mA ICHRG ,IACPR ,IEXTPWR ,IPBSTAT,IPGOOD..................75mA . IOVSENS..................................................................10mA ICLPROG,IPROG.........................................................2mA OperatingJunctionTemperatureRange (Note2)...............................................-40Cto85C MaximumJunctionTemperature...........................110C StorageTemperatureRange.................. -65Cto125C
orDer inForMaTion
LEAD FREE FINISH LTC3677EUFF-3#PBF TAPE AND REEL LTC3677EUFF-3#TRPBF PART MARKING 36773 PACKAGE DESCRIPTION 44-Lead(4mmx7mm)PlasticQFN TEMPERATURE RANGE -40Cto85C ConsultLTCMarketingforpartsspecifiedwithwideroperatingtemperatureranges. ConsultLTCMarketingforinformationonnon-standardleadbasedfinishparts. Formoreinformationonleadfreepartmarking,goto:http://www.linear.com/leadfree/ Formoreinformationontapeandreelspecifications,goto:http://www.linear.com/tapeandreel/
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LTC3677-3 elecTrical characTerisTics
SYMBOL VBUS IBUS_LIM IBUSQ hCLPROG VCLPROG VUVLO VDUVLO RON_ILIM Battery Charger VFLOAT ICHG IBATQ_OFF IBATQ_ON VPROG,CHG VPROG,TRKL hPROG ITRKL VTRKL VRECHRG tTERM tBADBAT hC/10 RON_CHG TLIM VBATRegulatedOutputVoltage LTC3677-3 LTC3677-3,0TJ85C
l l l
Power Manager. The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TJ = 25C. VBUS = 5V, VBAT = 3.8V, ILIM0 = ILIM1 = 5V, WALL = 0V, VINLDO2 = VINLOD1 = VIN12 = VIN3 = VOUT, RPROG = 2k, RCLPROG = 2.1k, unless otherwise noted.
PARAMETER InputSupplyVoltage TotalInputCurrent(Note5) ILIM0=5V,ILIM1=5V(1xMode) ILIM0=0V,ILIM1=0V(5xMode) ILIM0=0V,ILIM1=5V(10xMode) 1x,5x,10xModes ILIM0=5V,ILIM1=0V(SuspendMode)
l l l
CONDITIONS
MIN 4.35 80 450 900
TYP
MAX 5.5
UNITS V mA mA mA mA mA mA/mA V V V
Input Power Supply 90 475 950 0.42 0.05 1000 1xMode 5xMode 10xMode RisingThreshold FallingThreshold 3.5 0.2 1.0 2.0 3.8 3.7 50 -50 200 3.9 100 100 500 1000 0.1
InputQuiescentCurrent,POFFState RatioofMeasuredVBUSCurrentto CLPROGProgramCurrent CLPROGServoVoltageinCurrent Limit VBUSUndervoltageLockout
V V mV mV m
VBUStoVOUTDifferentialUndervoltage RisingThreshold Lockout FallingThreshold InputCurrentLimitPowerFET On-Resistance(BetweenVBUSandVOUT) 4.179 4.165 950 465 180
4.200 4.200 1000 500 200 6 55 130 1.000 0.100 1000
4.221 4.235 1050 535 220 27 100 200
V V mA mA mA A A A V V mA/mA
Constant-CurrentModeChargeCurrent RPROG=1k,InputCurrentLimit=2A ICNotinThermalLimit RPROG=2k,InputCurrentLimit=1A RPROG=5k,InputCurrentLimit=0.4A Battery-DrainCurrent,POFFState, Buck3Disabled,NoLoad(Note14) Battery-DrainCurrent,PONState, Buck3Enabled(Notes10,14) PROGPinServoVoltage PROGPinServoVoltageinTrickle Charge RatioofIBATtoPROGPinCurrent TrickleChargeCurrent TrickleChargeRisingThreshold TrickleChargeFallingThreshold RechargeBatteryThresholdVoltage SafetyTimerTerminationPeriod BadBatteryTerminationTime BatteryChargerPowerFET On-Resistance(BetweenVOUTandBAT) JunctionTemperatureinConstantTemperatureMode VBATVTRKL VBAT40 2.5 -75 3.2 0.4 0.085
50 2.9 2.75 -100 4 0.5 0.1 200 110
60 3.0 -125 4.8 0.6 0.11
mA V V mV Hour Hour mA/mA m C
End-of-ChargeIndicationCurrentRatio (Note6)
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LTC3677-3 elecTrical characTerisTics
SYMBOL VCOLD VHOT VTOO_HOT INTC IBAT2HOT VBAT2HOT Ideal Diode VFWD RDROPOUT IMAX VOVCUTOFF VOVGATE IOVSENSQ tRISE VACPR VW VW IQWALL ForwardVoltageDetection DiodeOn-Resistance,Dropout DiodeCurrentLimit OvervoltageProtectionThreshold OVGATEOutputVoltage OVSENSQuiescentCurrent OVGATETimetoReachRegulation ACPRPinOutputHighVoltage ACPRPinOutputLowVoltage AbsoluteWallInputThresholdVoltage DifferentialWallInputThreshold Voltage WallOperatingQuiescentCurrent IOUT=10mA IOUT=200mA (Note7) RisingThreshold,ROVSENS=6.2k InputBelowVOVCUTOFF InputAboveVOVCUTOFF VOVSENS=5V COVGATE=1nF IACPR=0.1mA IACPR=1mA VWALLRising VWALLFalling VWALL-VBATFalling VWALL-VBATRising IWALL+IVOUT,IBAT=0mA, WALL=VOUT=5V ILIM0,ILIM1 ILIM0,ILIM1 ILIM0,ILIM1;VPIN=1V ICHRG=10mA VBAT=4.5V,VCHRG=5V 1.2 2 0.15 0 0.4 1 VOUT-0.3 3.1 0 6.10 5 15 200 3.6 6.35 1.88*VOVSENS 0 40 2.5 VOUT 0 4.3 3.2 25 75 440 0.3 4.45 100 6.70 12 25 mV m A V V V A ms V V V V mV mV A PARAMETER ColdTemperatureFaultThreshold Voltage HotTemperatureFaultThreshold Voltage NTCDischargeThresholdVoltage NTCLeakageCurrent BATDischargeCurrent BATDischargeThreshold NTC, Battery Discharge Protection RisingNTCVoltage Hysteresis FallingNTCVoltage Hysteresis FallingNTCVoltage Hysteresis VNTC=VBUS=5V VBAT=4.1V,NTCPower Manager. The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TJ = 25C. VBUS = 5V, VBAT = 3.8V, ILIM0 = ILIM1 = 5V, WALL = 0V, VINLDO2 = VINLOD1 = VIN12 = VIN3 = VOUT, RPROG = 2k, RCLPROG = 2.1k, unless otherwise noted.
CONDITIONS MIN TYP MAX UNITS
Overvoltage Protection
Wall Adapter and High Voltage Buck Output Control
Logic (ILIM0, ILIM1 and CHRG) VIL VIH IPD VCHRG ICHRG InputLowVoltage InputHighVoltage StaticPull-DownCurrent CHRGPinOutputLowVoltage CHRGPinInputCurrent 0.4 V V A V A
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LTC3677-3 elecTrical characTerisTics
SYMBOL DVCC IDVCC VDVCC,UVLO VIH VIL IIH IIL VOL fSCL tLOW tHIGH tBUF tHD,STA tSU,STA tSU,STO tHD,DATO tHD,DATI tSU,DAT tSP PARAMETER InputSupplyVoltage DVCCSupplyCurrent DVCCUVLO InputHighVoltage InputLowVoltage InputHighLeakageCurrent InputLowLeakageCurrent SDAOutputLowVoltage SCLClockFrequency LowPeriodoftheSCLClock HighPeriodoftheSCLClock BusFreeTimeBetweenStopandStartCondition HoldTimeAfter(Repeated)StartCondition Set-UpTimeforaRepeatedStartCondition StopConditionSet-UpTime OutputDataHoldTime InputDataHoldTime DataSet-UpTime InputSpikeSuppressionPulseWidth 1.3 0.6 1.3 0.6 0.6 0.6 0 0 100 50 900 SDA=SCL=DVCC=5.5V SDA=SCL=0V,DVCC=5.5V ISDA=3mA 30 -1 -1 SCL=400kHz SCL=SDA=0kHz 1.0 50 50 1 1 0.4 400 70
I2C Interface. The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TJ = 25C. DVCC = 3.3V, VOUT = 3.8V, unless otherwise noted.
CONDITIONS MIN 1.6 TYP MAX 5.5 10 1 UNITS V A A V %DVCC %DVCC A A V kHz s s s s s s ns ns ns ns
Timing Characteristics (Note 8) (All Values Are Referenced to VIH and VIL)
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LTC3677-3 elecTrical characTerisTics
SYMBOL VIN12,VIN3 VOUTUVLO fOSC IVIN3Q PARAMETER InputSupplyVoltage VOUTFalling VOUTRising OscillatorFrequency Pulse-SkippingModeInputCurrent BurstModeOperationInputCurrent ShutdownInputCurrent ILIM3 VFB3 IFB3 D3 RP3 RN3 RSW3_PD VIL,EN3 VIH,EN3 IVIN12Q PeakP-ChannelMOSFETCurrentLimit FeedbackVoltage FB3InputCurrent MaxDutyCycle RDS(ON)ofP-ChannelMOSFET RDS(ON)ofN-ChannelMOSFET SW3Pull-DowninShutdown EN3InputLowVoltage EN3InputHighVoltage Pulse-SkippingModeInputCurrent BurstModeOperationInputCurrent ShutdownInputCurrent ILIM2 VFB2 IFB2 D2 RP2 RN2 RSW2_PD IVIN12Q PeakP-ChannelMOSFETCurrentLimit FeedbackVoltage FB2InputCurrent MaxDutyCycle RDS(ON)ofP-ChannelMOSFET RDS(ON)ofN-ChannelMOSFET SW2Pull-DowninShutdown Pulse-SkippingModeInputCurrent BurstModeOperationInputCurrent ShutdownInputCurrent ILIM1 VFB1 IFB1 D1 RP1 RN1 RSW1_PD PeakP-ChannelMOSFETCurrentLimit FeedbackVoltage FB1InputCurrent MaxDutyCycle RDS(ON)ofP-ChannelMOSFET RDS(ON)ofN-ChannelMOSFET SW1Pull-DowninShutdown (Note7) Pulse-SkippingMode BurstModeOperation (Note10) FB1=0V ISW1=100mA ISW1=-100mA POFFState
l l
Step-Down Switching Regulators. The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TJ = 25C. VOUT = VIN12 = VIN3 = 3.8V, all regulators enabled unless otherwise noted.
CONDITIONS (Note9) VIN12andVIN3ConnectedtoVOUTThrough LowImpedance.SwitchingRegulatorsAre DisabledBelowVOUTUVLO (Note10) (Note10) EN3=0 (Note7) Pulse-SkippingMode BurstModeOperation (Note10) FB3=0V
l l l
MIN 2.7 2.5
TYP
MAX 5.5
UNITS V V V MHz A
Step-Down Switching Regulators (Buck1, Buck2 and Buck3) 2.7 2.8 2.25 100 20 0.01 1000 0.78 0.78 -0.05 100 0.3 0.4 EN3=0 1.2 (Note10) (Note10) POFFState (Note7) Pulse-SkippingMode BurstModeOperation (Note10) FB2=0V ISW2=100mA ISW2=-100mA POFFState (Note10) (Note10) 650 0.78 0.78 -0.05 100 0.6 0.6 10
l l
2.9 2.59
1.91
800mA Step-Down Switching Regulator 3 (Buck3-Enabled via EN3, Disabled in PDN and POFF States) 35 1 1700 0.82 0.824 0.05 A A mA V V A % k 0.4 V V 100 20 0.01 650 0.78 0.78 -0.05 100 0.6 0.6 10 100 20 0.01 900 0.8 0.8 1 1200 0.82 0.824 0.05 900 0.8 0.8 1 1200 0.82 0.824 0.05 A A A mA V V A % k A A A mA V V A % k
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1400 0.8 0.8
10
500mA Step-Down Switching Regulator 2 (Buck2-Pushbutton Enabled, Third in Sequence)
500mA Step-Down Switching Regulator 1 (Buck1-Pushbutton Enabled, Second in Sequence)
LTC3677-3 elecTrical characTerisTics
SYMBOL VINLDO1 VOUT_UVLO VLDO1_FB PARAMETER InputVoltageRange VOUTFalling VOUTRising LDO1_FBRegulatedFeedbackVoltage LDO1_FBLineRegulation(Note11) LDO1_FBLoadRegulation(Note11) ILDO1_OC ILDO1_SC VDROP1 RLDO1_PD ILDO_FB1 VINLDO2 VOUT_UVLO VLDO2_FB AvailableOutputCurrent Short-CircuitOutputCurrent(Note7) DropoutVoltage(Note12) ILDO1=150mA,VINLDO1=3.6V ILDO1=150mA,VINLDO1=2.5V ILDO1=75mA,VINLDO1=1.8V LDO1Disabled -50 VINLDO2VOUT+0.3V LDO2isDisabledBelowVOUTUVLO ILDO2=1mA ILDO2=1mA,VIN=1.65Vto5.5V ILDO2=1mAto150mA
l l l
LDO Regulators. The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TJ = 25C. VINLDO1 = VINLDO2 = VOUT = 3.8V, LDO1 and LDO2 enabled unless otherwise noted.
CONDITIONS VINLDO1VOUT+0.3V LDO1IsDisabledBelowVOUTUVLO ILDO1=1mA ILDO1=1mA,VIN=1.65Vto5.5V ILDO1=1mAto150mA
l l l
MIN 1.65 2.5 0.78
TYP
MAX 5.5
UNITS V V V V mV/V V/mA mA mA
LDO Regulator 1 (LDO1-Always On) 2.7 2.8 0.8 0.4 5 150 270 160 200 170 10 50 5.5 2.7 2.8 0.8 0.4 5 150 270 ILDO2=150mA,VINLDO2=3.6V ILDO2=150mA,VINLDO2=2.5V ILDO1=75mA,VINLDO1=1.8V LDO2Disabled -50 160 200 170 14 50 260 320 280 2.9 0.82 260 320 280 2.9 0.82
mV mV mV k nA V V V V mV/V V/mA mA mA mV mV mV k nA
OutputPull-DownResistanceinShutdown LDO_FB1InputCurrent InputVoltageRange VOUTFalling VOUTRising LDO2_FBRegulatedOutputVoltage LDO2_FBLineRegulation(Note11) LDO2_FBLoadRegulation(Note11)
LDO Regulator 2 (LDO2-Pushbutton Enabled, First in Sequence) 1.65 2.5 0.78
ILDO2_OC ILDO2_SC VDROP2 RLDO2_PD ILDO_FB2
AvailableOutputCurrent Short-CircuitOutputCurrent(Note7) DropoutVoltage(Note12)
OutputPull-DownResistanceinShutdown LDO_FB2InputCurrent
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LTC3677-3 elecTrical characTerisTics
SYMBOL VOUT VOUTUVLO VON_TH ION PARAMETER PushbuttonOperatingSupplyRange VOUTFalling VOUTRising ONThresholdRising ONThresholdFalling ONInputCurrent VON=VOUT VON=0V Pushbutton Pin (ON) (Note9) PushbuttonisDisabledBelowVOUTUVLO
l
Pushbutton Controller. The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TJ = 25C. VOUT = 3.8V, unless otherwise noted.
CONDITIONS MIN 2.7 2.5 0.4 -1 -4 0.4 VPWR_ON=3V VPBSTAT=3V IPBSTAT=3mA VEXTPWR=3V IEXTPWR=2mA VPGOOD=3V IPGOOD=3mA (Note13) -1 0.1 -8 50 PBSTATLow>tPBSTAT_PW 40 12 900 50 50 14 1.8 1 1 50 50 PWR_ONLowRecognizedfromPower-Up PWR_ONHighRecognizedfromPower-Down Buck1,2andLDO1WithinPGOODThreshold BucksDisabled 12.5 1 1 230 44 14.5 17.5 16.5 -1 -1 0.1 0 0.15 2.7 2.8 0.8 0.7 -9 0.8 0.7 TYP MAX 5.5 2.9 1.2 1 -14 1.2 1 1 0.4 1 0.4 1 0.4 UNITS V V V V V A A V V A A V A V A V % ms s ms ms Seconds ms Seconds Seconds ms ms Seconds Seconds ms s ms
Power-On Input Pin (PWR_ON) VPWR_ON IPWR_ON IPBSTAT VPBSTAT IEXTPWR VEXTPWR IPGOOD VPGOOD VTHPGOOD tON_PBSTAT1 tON_PBSTAT2 tPBSTAT_PW tON_PUP tON_RST tON_RST_PW tPUP_PDN tPDN_PUP tPWR_ONH tPWR_ONL tPWR_ONBK1 tPWR_ONBK2 tPGOODH tPGOODL tLDO2_BK1 PWR_ONThresholdRising PWR_ONThresholdFalling PWR_ONInputCurrent PBSTATOutputHighLeakageCurrent PBSTATOutputLowVoltage EXTPWRPinInputCurrent EXTPWRPinOutputLowVoltage PGOODOutputHighLeakageCurrent PGOODOutputLowVoltage PGOODThresholdVoltage ONLowTimetoPBSTATLow ONHightoPBSTATHigh PBSTATMinimumPulseWidth ONLowTimeforPower-Up ONLowtoPGOODResetLow PGOODResetLowPulseWidth MinimumTimefromPowerUptoDown MinimumTimefromPowerDowntoUp PWR_ONHightoPower-Up PWR_ONLowtoPower-Down PWR_ONPower-UpBlanking PWR_ONPower-DownBlanking FromRegulationtoPGOODHigh BucksDisabledtoPGOODLow LDO2EnabletoBuckEnable
Status Output Pins (PBSTAT, EXTPWR, PGOOD)
Pushbutton Timing Parameters
Note 1:StressesbeyondthoselistedunderAbsoluteMaximumRatings maycausepermanentdamagetothedevice.ExposuretoanyAbsolute MaximumRatingconditionforextendedperiodsmayaffectdevice reliabilityandlifetime. Note 2:TheLTC3677-3isguaranteedtomeetperformancespecifications from0Cto85C.Specificationsoverthe-40Cto85Coperating junctiontemperaturerangeareassuredbydesign,characterizationand correlationwithstatisticalprocesscontrols.Notethatthemaximum
ambienttemperatureisdeterminedbyspecificoperatingconditionsin conjunctionwithboardlayout,theratedpackagethermalresistanceand otherenvironmentalfactors. Note 3:ThisICincludesovertemperatureprotectionthatisintended toprotectthedeviceduringmomentaryoverloadconditions.Junction temperatureswillexceed110Cwhenovertemperatureprotectionis active.Continuousoperationabovethespecifiedmaximumoperating junctiontemperaturemayresultindevicedegradationorfailure.
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LTC3677-3 elecTrical characTerisTics
Note 4:VCCisthegreaterofVBUS,VOUTorBAT. Note 5:Totalinputcurrentisthesumofquiescentcurrent,IBUSQ,and measuredcurrentgivenbyVCLPROG/RCLPROG*(hCLPROG+1). Note 6:hC/10isexpressedasafractionofmeasuredfullchargecurrent withindicatedPROGresistor. Note 7:Thecurrentlimitfeaturesofthispartareintendedtoprotectthe ICfromshorttermorintermittentfaultconditions.Continuousoperation abovethemaximumspecifiedpincurrentratingmayresultindevice degradationorfailure. Note 8:Theserialportistestedatratedoperatingfrequency.Timing parametersaretestedand/orguaranteedbydesign. Note 9:VOUTnotinUVLO. Note 10:BuckFBhigh,notswitching. Note 11:MeasuredwiththeLDOrunningunitygainwithoutputtiedto feedbackpin. Note 12:Dropoutvoltageistheminimuminputtooutputvoltage differentialneededforanLDOtomaintainregulationataspecifiedoutput current.WhenanLDOisindropout,itsoutputvoltagewillbeequalto VIN-VDROP. Note 13:PGOODthresholdisexpressedasapercentagedifference fromtheBuck1,Buck2andLDO1regulationvoltages.Thethresholdis measuredfromBuck1,Buck2andLDO1outputrising. Note 14:TheIBATQspecificationsrepresentthetotalbatteryloadassuming VINLDO1,VINLDO2,VIN12andVIN3aretieddirectlytoVOUT. Note 15:Long-termcurrentdensityratingforthepart.
Typical perForMance characTerisTics TJ = 25C unless otherwise specified
Input Supply Current vs Temperature
0.8 0.7 0.6 IVBUS (mA) IVBUS (mA) 0.5 0.4 0.3 0.2 0.1 0 -50 -25 0 50 75 25 TEMPERATURE (C) 100 125
36773 G01
Input Supply Current vs Temperature (Suspend Mode)
0.10 VBUS = 5V 450 400 350 300 IBAT (A) 0.06 250 200 150 0.02 100 50 0 -50 -25 50 25 0 75 TEMPERATURE (C) 100 125
Battery-Drain Current vs Temperature
ALL SUPPLIES ENABLED PULSE-SKIPPING MODE NO LOAD ON ALL SUPPLIES VBAT = 3.8V VBUS = 0V ALL SUPPLIES ENABLED Burst Mode OPERATION
VBUS = 5V 1x MODE
0.08
0.04
0 -50
ALL SUPPLIES DISABLED EXCEPT LDO1 -25 50 25 0 75 TEMPERATURE (C) 100 125
36773 G03
36773 G02
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0
LTC3677-3 Typical perForMance characTerisTics TJ = 25C unless otherwise specified
1200 1100 1000 900 800 IVBUS (mA) 600 500 400 300 200 100 0 -50 -25 1x MODE 50 25 0 75 TEMPERATURE (C) 100 125
36773 G04
Input Current Limit vs Temperature
VBUS = 5V RCLPROG = 2.1k 300 10x MODE 280 260 240 RON (m ) 220 180 160 140 120 100
Input RON vs Temperature
IOUT = 400mA
600 500
Charge Current vs Temperature (Thermal Regulation)
VBUS = 4.5V IBAT (mA) VBUS = 5V VBUS = 5.5V
400 300 200 100 VBUS = 5V 10x MODE RPROG = 2k 50 25 75 0 TEMPERATURE (C) 100 125
700 5x MODE
0 -50
-25
50 25 0 75 TEMPERATURE (C)
100
125
36773 G05
0 -50 -25
357734 G06
Battery Current and Voltage vs Time
600 500 400 IBAT (mA) 300 200 CHRG VBAT 4 3 SAFETY TIMER 2 TERMINATION C/10 IBAT 3 4 TIME (HOUR) 5 6
36773 G07
Battery Float Voltage Load Regulation
6 5 VBAT AND VCHRG (V) 4.24 4.22 4.20 VBAT (V) 4.18 4.16 4.14 4.12 4.10 0 200 400 600 800 1000
357734 G08
Battery Regulation (Float) Voltage vs Temperature
4.24 4.22 4.20 4.18 4.16 4.14 4.12 4.10 4.08 4.06 4.04 -50 -25 0 50 75 25 TEMPERATURE (C) 100 125
36773 G09
VBUS = 5V 10x MODE
IBAT = 2mA
1450mAhr CELL 100 VBUS = 5V RPROG = 2k RCLPROG = 2k 0 0 2 1
1 0
VFLOAT (V)
IBAT (mA)
IBAT vs VBAT
600 500 400 IBAT (mA) 300 200 100 0 0.25
Forward Voltage vs Ideal Diode Current (No External FET)
VBUS = 0V TA = 25C 40 VBAT = 3.2V VBAT = 3.6V VFWD (mV) VBAT = 4.2V 35 30 25 20 15 10 5 0 0.2 0.4 0.6 IBAT (A) 0.8 1.0 1.2
36773 G11
Forward Voltage vs Ideal Diode Current (with Si2333DS External FET)
VBAT = 3.8V VBUS = 0V TA = 25C
0.20 RISING VBAT FALLING VBAT VBUS = 5V 10x MODE RPROG = 2k RCLPROG = 2k 2.0 2.4 2.8 3.2 3.6 VBAT (V) 4.0 4.4
36773 G10
VFWD (V)
0.15
0.10
0.05 0
0
0
0.2
0.4
0.6 IBAT (A)
0.8
1.0
36773 G12
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LTC3677-3 Typical perForMance characTerisTics TJ = 25C unless otherwise specified
Input Connect Waveform
VBUS 5V/DIV VOUT 5V/DIV IBUS 0.5A/DIV IBAT 0.5A/DIV VBAT = 3.75V IOUT = 100mA RCLPROG = 2k RPROG = 2k 1ms/DIV
36773 G13
Input Disconnect Waveform
VBUS 5V/DIV VOUT 5V/DIV IBUS 0.5A/DIV IBAT 0.5A/DIV VBAT = 3.75V IOUT = 100mA RCLPROG = 2k RPROG = 2k 1ms/DIV
36773 G14
Switching from 1x to 5x Mode
ILIM0/ILIM1 5V/DIV IBUS 0.5A/DIV IBAT 0.5A/DIV VBAT = 3.75V IOUT = 50mA RCLPROG = 2k RPROG = 2k 1ms/DIV
36773 G15
Switching from Suspend Mode to 5x Mode
ILIM0 5V/DIV VOUT 5V/DIV IBUS 0.5A/DIV IBAT 0.5A/DIV VBAT = 3.75V IOUT = 100mA RCLPROG = 2k RPROG = 2k ILIM1 = 5V 100s/DIV
36773 G16
WALL Connect Waveform
WALL 5V/DIV VOUT 5V/DIV IWALL 0.5A/DIV IBAT 0.5A/DIV VBAT = 3.75V IOUT = 100mA RPROG = 2k 1ms/DIV
36773 G17
WALL Disconnect Waveform
WALL 5V/DIV VOUT 5V/DIV IWALL 0.5A/DIV IBAT 0.5A/DIV VBAT = 3.75V IOUT = 100mA RPROG = 2k 1ms/DIV
36773 G18
Oscillator Frequency vs Temperature
2.8 2.7 2.6 FREQUENCY (MHz) 2.4 2.3 2.2 2.1 2.0 1.9 1.8 -50 -25 50 25 0 75 TEMPERATURE (C) 100 125
36773 G19
100
Step-Down Switching Regulator 1 3.3V Output Efficiency vs IOUT1
Burst Mode 90 OPERATION 80 70 60 50 40 30
VOUT = 5V VOUT = 3.8V
EFFICIENCY (%)
2.5
PULSE-SKIPPING
20 10 0 0.01 0.1 1 10 IOUT (mA)
VOUT1 = 3.3V VIN12 = 3.8V VIN12 = 5V 100 1000
36773 G20
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LTC3677-3 Typical perForMance characTerisTics TJ = 25C unless otherwise specified
100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 0.01 0.1 1 10 IOUT (mA) VOUT2 = 1.8V VIN12 = 3.8V VIN12 = 5V 100 1000
36773 G21
Step-Down Switching Regulator 2 1.8V Output Efficiency vs IOUT2
Burst Mode OPERATION EFFICIENCY (%) PULSE-SKIPPING
100 90 80 70 60 50 40 30 20 10
Step-Down Switching Regulator 3 1.2V Output Efficiency vs IOUT3
Burst Mode OPERATION EFFICIENCY (%)
Step-Down Switching Regulator 3 2.5V Output Efficiency
100 90 80 70 60 50 40 30 20 10 0 0.01 0.1 1 10 IOUT (mA) VOUT3 = 2.5V VIN3 = 3.8V VIN3 = 5V 100 1000
36773 G23
Burst Mode OPERATION
PULSE-SKIPPING
PULSE-SKIPPING
0 0.01
VOUT3 = 1.2V VIN3 = 3.8V VIN3 = 5V 0.1 1 10 IOUT (mA) 100 1000
36773 G22
Step-Down Switching Regulator Short-Circuit Current vs Temperature
1500 1400 SHORT-CIRCUIT CURRENT (mA) 1300 1200 1100 1000 900 800 700 600 500 -50 -25 0 VINx = 3.8V VINx = 5V 50 75 25 TEMPERATURE (C) 100 125
36773 G24
Step-Down Switching Regulator Output Transient (Burst Mode Operation)
VOUT1 50mV/DIV (AC) VOUT2 50mV/DIV (AC) VOUT3 100mV/DIV (AC) IOUT3 500mA 5mA VOUT1 = 3.3V 50s/DIV IOUT1 = 10mA VOUT2 = 1.8V IOUT2 = 20mA VOUT3 = 1.2V VOUT = VBAT = 3.8V
36773 G25
Step-Down Switching Regulator Output Transient (Pulse-Skipping)
VOUT1 50mV/DIV (AC) VOUT2 50mV/DIV (AC) VOUT3 100mV/DIV (AC) IOUT3 500mA 5mA VOUT1 = 3.3V 50s/DIV IOUT1 = 30mA VOUT2 = 1.8V IOUT2 = 20mA VOUT3 = 1.2V VOUT = VBAT = 3.8V
36773 G26
800mA BUCK
500mA BUCK
Step-Down Switching Regulator Switch Impedance vs Temperature
0.9 0.8 SWITCH IMPEDANCE ( ) 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -50 -25 0 25 50 75 TEMPERATURE (C) 100 125
36773 G27
800mA Step-Down Switching Regulator Feedback Voltage vs Output Current
0.85 0.84 0.85 0.84 0.83 FEEDBACK (V) Burst Mode OPERATION PULSE-SKIPPING 0.82 0.81 0.80 0.79 0.78 0.77 VIN3 = 3.8V VIN3 = 5V 1 10 IOUT (mA) 100 1000
357732 G29
500mA Step-Down Switching Regulator Feedback Voltage vs Output Current
VINX = 3.2V 500mA PMOS FEEDBACK (V)
0.83 0.82 0.81 0.80 0.79 0.78 0.77 0.76 0.75 0.1
500mA NMOS
Burst Mode OPERATION PULSE-SKIPPING
800mA PMOS 800mA NMOS
0.76 0.75 0.1 1 10 IOUT (mA)
VIN12 = 3.8V VIN12 = 5V 100 1000
36773 G29
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LTC3677-3 Typical perForMance characTerisTics TJ = 25C unless otherwise specified
Step-Down Switching Regulator 3 Soft-Start and Shutdown
VOUT1 100mV/DIV (AC) 2V VOUT3 1V 0V 400mA IL3 200mA 0mA VOUT1 = 1.8V IOUT1 = 100mA ROUT3 = 3 50s/DIV
36773 G30
OVP Connection Waveform
VBUS 5V/DIV
OVGATE 5V/DIV OVP INPUT VOLTAGE 0V TO 5V STEP 5V/DIV
500s/DIV
36773 G31
OVP Protection Waveform
VBUS 5V/DIV OVGATE 5V/DIV OVP INPUT VOLTAGE 5V TO 10V STEP 5V/DIV 500s/DIV
36773 G32
OVP Reconnection Waveform
VBUS 5V/DIV
OVGATE 5V/DIV OVP INPUT VOLTAGE 10V TO 5V STEP 5V/DIV
500s/DIV
36773 G33
OVSENS Quiescent Current vs Temperature
37 VOVSENS = 5V 6.280
Rising Overvoltage Threshold vs Temperature
QUIESCENT CURRENT (A)
35 OPV THRESHOLD (V) -15 35 10 TEMPERATURE (C)
6.275
33
6.270
31 29
6.265 6.260
27 -40
60
85
36773 G34
6.255 -40
-15
35 10 TEMPERATURE (C)
60
85
36773 G35
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LTC3677-3 Typical perForMance characTerisTics TJ = 25C unless otherwise specified
OVGATE vs OVSENS
12 OVSENS CONNECTED TO INPUT THROUGH 10 6.2k RESISTOR 8 OVGATE (V) 6 4 IOUT1 2 0 LDO2 20mV/DIV (AC) 100mA 5mA LDO1 = 1.2V 20s/DIV LDO2 = 2.5V ILDO2 = 40mA VOUT = VBAT = 3.8V
36773 G37
LDO Load Step
200 LDO1 50mV/DIV (AC) IBAT (mA)
Too Hot BAT Discharge
VNTC < VTOO_HOT 180 VBUS = 0V 160 140 120 100 80 60 40 20 0 3.8 3.9 4.0 VBAT (V) 4.1 4.2
36773 G38
0
2
4 6 INPUT VOLTAGE (V)
8
36773 G36
Battery Discharge vs Temperature
200 BATTERY DISCHARGE CURRENT (mA) 175 150 125 100 75 50 25 0 50 VBAT = 4.1V VNTC < VTOO_HOT 5x MODE IVOUT = 0mA 60 70 90 100 80 TEMPERATURE (C) 110 120
36773 G39
Input and Battery Current vs Output Current
600 500 400 CURRENT (mA) RPROG = 2k RCLPROG = 2k IIN
VBUS = 5V
ILOAD
VBUS = 0V
300 200 100 0 -100 WALL = 0V 0 100 200 IBAT (DISCHARGING) 400 300 IOUT (mA) 500 600
36773 G40
IBAT (CHARGING)
pin FuncTions
ILIM0, ILIM1 (Pins 1, 2):InputCurrentControlPins.ILIM0 andILIM1controltheinputcurrentlimit.SeeTable1inthe USBPowerPathControllersection.Bothpinsarepulled lowbyaweakcurrentsink. NC (Pins 3, 9, 18, 19, 20, 22):NoConnect.Thispinhas nofunctionandmaybefloatedorconnectedtoground. WALL (Pin 4):WallAdapterPresentInput.Pullingthis pinabove4.3VwilldisconnectthepowerpathfromVBUS toVOUT.TheACPRpinwillalsobepulledlowtoindicate thatawalladapterhasbeendetected. SW3 (Pin 5):PowerTransmission(Switch)PinforStepDownSwitchingRegulator3(Buck3). VIN3 (Pin 6):PowerInputforStep-DownSwitchingRegulator3.ThispinshouldbeconnectedtoVOUT. FB3 (Pin 7): Feedback Input for Step-Down Switching Regulator3(Buck3).Thispinservostoafixedvoltageof 0.8Vwhenthecontrolloopiscomplete. OVSENSE (Pin 8):OvervoltageProtectionSenseInput. OVSENSEshouldbeconnectedthrougha6.2kresistor totheinputpowerconnectorandthedrainofanexternal
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LTC3677-3 pin FuncTions
N-channelMOSFETpasstransistor.Whenthevoltageon thispinexceedsapresetlevel,theOVGATEpinwillbe pulledtoGNDtodisablethepasstransistorandprotect downstreamcircuitry. DVCC (Pin 10):SupplyVoltageforI2CLines.Thispinsets thelogicreferenceleveloftheLTC3677-3.AUVLOcircuit ontheDVCCpinforcesallregisterstoall0swheneverDVCC is<1V.BypasstoGNDwitha0.1Fcapacitor. SDA (Pin 11):I2CDataInput.Serialdataisshiftedone bitperclocktocontroltheLTC3677-3.Thelogiclevelfor SDAisreferencedtoDVCC. SCL (Pin referencedtoDVCC. 12):I2CClockInput.ThelogiclevelforSCLis value.Thereisa230msdelayfromallregulatorsreaching regulationandPGOODgoinghigh. LDO1_FB (Pin 23):FeedbackVoltageInputforLowDropoutLinearRegulator1(LDO1).LDO1outputvoltageis setusinganexternalresistordividerbetweenLDO1and LDO1_FB. LDO2_FB (Pin 24):FeedbackVoltageInputforLowDropoutLinearRegulator2(LDO2).LDO2outputvoltageis setusinganexternalresistordividerbetweenLDO2and LDO2_FB. FB2 (Pin 25):FeedbackInputforStep-DownSwitching Regulator2(Buck2).Thispinservostoafixedvoltageof 0.8Vwhenthecontrolloopiscomplete. FB1 (Pin 26):FeedbackInputforStep-DownSwitching Regulator1(Buck1).Thispinservostoafixedvoltageof 0.8Vwhenthecontrolloopiscomplete. VINLDO1 (Pin 27): Input Supply of Low Dropout Linear Regulator1(LDO1).Thispinshouldbebypassedtoground witha1Forgreaterceramiccapacitor. LDO1 (Pin 28):OutputofLowDropoutLinearRegulator1. LDO1isanalways-onLDOandwillbeenabledwhenever thepartisnotinVOUTUVLO.Thispinmustbebypassed togroundwitha1Forgreaterceramiccapacitor. LDO2 (Pin 29):OutputofLowDropoutLinearRegulator2. Thispinmustbebypassedtogroundwitha1Forgreater ceramiccapacitor. VINLDO2 (Pin 30): Input Supply of Low Dropout Linear Regulator2(LDO2).Thispinshouldbebypassedtoground witha1Forgreaterceramiccapacitor. SW2 (Pin 31):PowerTransmission(Switch)PinforStepDownSwitchingRegulator2(Buck2). VIN12 (Pin 32): Power Input for Step-Down Switching Regulators1and2.Thispinwillgenerallybeconnected toVOUT. SW1 (Pin 33):PowerTransmission(Switch)PinforStepDownSwitchingRegulator1(Buck1). NTCBIAS (Pin 34): Output Bias Voltage for NTC. A resistorfromthispintotheNTCpinwillbiastheNTC thermistor.
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OVGATE (Pin 13): Overvoltage Protection Gate Output. ConnectOVGATEtothegatepinofanexternalN-channel MOSFETpasstransistor.Thesourceofthetransistorshould beconnectedtoVBUSandthedrainshouldbeconnected totheproduct'sDCinputconnector.Intheabsenceofan overvoltagecondition,thispinisconnectedtoaninternal chargepumpcapableofcreatingsufficientoverdriveto fullyenhancethistransistor.Ifanovervoltagecondition isdetected,OVGATEisbroughtrapidlytoGNDtoprevent damage.OVGATEworksinconjunctionwithOVSENSEto providethisprotection. PWR_ON (Pin 14):LogicInputUsedtoKeepBuck1,Buck2 andLDO2EnabledAfterPower-Up.Mayalsobeusedto enableregulatorsdirectly(sequence=LDO2Buck1 Buck2).SeethePushbuttonInterfaceOperationsection formoreinformation. ON (Pin 15):PushbuttonInput.Aweakinternalpull-up forcesONhighwhenleftfloating.AnormallyopenpushbuttonisconnectedfromONtogroundtoforcealow stateonthispin. PBSTAT (Pin 16): Open-drain output is a debounced and buffered version of ON to be used for processor interrupts. EN3 (Pin 17): Enable Pin for Step-Down Switching Regulator3(Buck3). PGOOD (Pin 21):Open-DrainOutput.PGOODindicatesthat Buck1,Buck2andLDO1arewithin8%offinalregulation
LTC3677-3 pin FuncTions
NTC (Pin 35):TheNTCpinconnectstoabattery'sthermistor to determine if the battery is too hot or too cold to charge. If the battery's temperature is out of range, chargingispauseduntilitdropsbackintorange.Alow driftbiasresistorisrequiredfromNTCBIAStoNTCand athermistorisrequiredfromNTCtoground. PROG (Pin 36): Charge Current Program and Charge CurrentMonitorPin.ConnectingaresistorfromPROG togroundprogramsthechargecurrent: ICHG = 1000 V A RPROG walladapter.VBUSshouldbebypassedwithalowimpedancemultilayerceramiccapacitor. ACPR (Pin 41):WallAdapterPresentOutput(ActiveLow). Alowonthispinindicatesthatthewalladapterinputcomparatorhashaditsinputpulledaboveitsinputthreshold (typically4.3V).Thispincanbeusedtodrivethegateof anexternalP-channelMOSFETtoprovidepowertoVOUT fromapowersourceotherthanaUSBport. EXTPWR (Pin 42):ExternalPowerPresentOutput(Active Low,Open-DrainOutput).Alowonthispinindicatesthat externalpowerispresentateithertheVBUSorWALLinput. ForEXTPWRtosignalVBUSpresent,VBUSmustexceed theVBUSundervoltagelockoutthreshold.ForEXTPWRto signalWALLpresent,WALLmustexceedtheabsoluteand differentialWALLinputthresholds.TheEXTPWRsignalis independentoftheILIM1andILIM0pins.Thus,itispossible tohavetheinputcurrentlimitcircuitryinsuspendwith EXTPWRshowingavalidcharginglevelonVBUS. CLPROG (Pin 43): Input Current Program and Input CurrentMonitorPin.AresistorfromCLPROGtoground determinestheupperlimitofthecurrentdrawnfromthe VBUSpin(i.e.,theinputcurrentlimit).Aprecisefraction oftheinputcurrent,hCLPROG,issenttotheCLPROGpin. TheinputPowerPathdeliverscurrentuntiltheCLPROG pinreaches2V(10xmode),1V(5xmode)or0.2V(1x mode).Therefore,thecurrentdrawnfromVBUSwillbe limitedtoanamountgivenbyhCLPROGandRCLPROG.In USBapplicationstheresistorRCLPROGshouldbesetto nolessthan2.1k. CHRG (Pin 44):Open-DrainChargeStatusOutput.The CHRGpinindicatesthestatusofthebatterycharger.If CHRGishighthenthechargerisnearthefloatvoltage (chargecurrentlessthan1/10thprogrammedchargecurrent)orchargingiscompleteandchargerisdisabled.Alow onCHRGindicatesthatthechargerisenabled.Formore informationseetheChargeStatusIndicationsection. GND (Exposed Pad Pin 45):Theexposedpackagepadis groundandmustbesolderedtoPCBgroundforelectrical contactandratedthermalperformance.
()
Ifsufficientinputpowerisavailableinconstant-current mode,thispinservosto1V.Thevoltageonthispinalways representstheactualchargecurrent. IDGATE (Pin 37): Ideal Diode Gate Connection. This pincontrolsthegateofanoptionalexternalP-channel MOSFETtransistorusedtosupplementtheinternalideal diode.ThesourceoftheP-channelMOSFETshouldbe connectedtoVOUTandthedrainshouldbeconnectedto BAT.Itisimportanttomaintainhighimpedanceonthis pinandminimizeallleakagepaths. BAT (Pin 38):Single-CellLi-IonBatteryPin.Depending onavailablepowerandload,aLi-IonbatteryonBATwill either deliver system power to VOUT through the ideal diodeorbechargedfromthebatterycharger. VOUT (Pin 39):OutputVoltageofthePowerPathController andInputVoltageoftheBatteryCharger.Themajorityof theportableproductshouldbepoweredfromVOUT.The LTC3677-3willpartitiontheavailablepowerbetweenthe external load on VOUT and the internal battery charger. Priorityisgiventotheexternalloadandanyextrapower isusedtochargethebattery.AnidealdiodefromBAT to VOUT ensures that VOUT is powered even if the load exceedstheallottedinputcurrentfromVBUSoriftheVBUS powersourceisremoved.VOUTshouldbebypassedwith alowimpedancemultilayerceramiccapacitor. VBUS (Pin 40):USBInputVoltage.VBUSwillusuallybe connectedtotheUSBportofacomputeroraDCoutput
36773f
LTC3677-3 block DiagraM
8 OVSENS OVERVOLTAGE PROTECTON 40 VBUS 13 OVGATE 42 EXTPWR EXTERNAL POWER DETECT 4 WALL WALL DETECT VOUT 39 41 ACPR
43 34 35 1 2 44
CLPROG NTCBIAS NTC ILIM0 ILIM1 CHRG CHARGE STATUS ILIM LOGIC 14ms RISING DELAY
BATTERY TEMP MONITOR
OVERTEMP BATTERY SAFETY DISCHARGER UVLO EN 150mA LDO2
0.8V
14 15 16 17 10 11 12 21
PWR_ON ON PBSTAT EN3 DVCC SDA SCL PGOOD 230ms FALLING DELAY LOGIC I2C PUSHBUTTON INPUT
EN 500mA, 2.25MHz BUCK REGULATOR 1 0.8V
+ -
PG EN 500mA, 2.25MHz BUCK REGULATOR 2 0.8V
+ -
PG EN 800mA, 2.25MHz BUCK REGULATOR 3
NC 3, 9, 18, 19, 20, 22
0.8V
+ -
0.8V
150mA LDO1 GND 45
+ -
ENB PG
+ - + -
INPUT CURRENT LIMIT
CC/CV CHARGER
IDEAL DIODE
+ -
15mV
IDGATE
37
BAT PROG
38 36
VINLD02
30
LDO2 LDO2_FB VIN12 SW1
29 24
32 33
FB1
26
SW2
31
FB2 VIN3 SW3
25 6 5
FB3 VINLD01
7 27
LDO1 LDO1_FB
28 23
36773 BD
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LTC3677-3 operaTion
PowerPath OPERATION Introduction TheLTC3677-3ishighlyintegratedpowermanagement ICthatincludesthefollowingfeatures: -PowerPathcontroller -Batterycharger -Idealdiode -Inputovervoltageprotection -Pushbuttoncontroller -Threestep-downswitchingregulators -Twolowdropoutlinearregulators DesignedspecificallyforUSBapplications,thePowerPath controller incorporates a precision input current limit whichcommunicateswiththebatterychargertoensure thatinputcurrentdoesnotviolatetheUSBaverageinput currentspecification.TheidealdiodefromBATtoVOUT guaranteesthatamplepowerisalwaysavailabletoVOUT evenifthereisinsufficientorabsentpoweratVBUS.The LTC3677-3alsohastheabilitytoreceivepowerfroma walladapterorothernon-current-limitedpowersource. SuchapowersupplycanbeconnectedtotheVOUTpinof theLTC3677-3throughanexternaldevicesuchasapower SchottkyorFET,asshowninFigure1.TheLTC3677-3has theuniqueabilitytousetheoutput,whichispoweredbyan externalsupply,tochargethebatterywhileprovidingpower totheload.AcomparatorontheWALLpinisconfigured todetectthepresenceofthewalladapterandshutoffthe connectiontotheUSB.Thispreventsreverseconduction fromVOUTtoVBUSwhenawalladapterispresent. TheLTC3677-3alsoincludesapushbuttoninputtocontrol the power sequencing of two synchronous step-down switchingregulators(Buck1andBuck2),alowdropout regulator(LDO2)andsystemreset.Thethree2.25MHz constant-frequency current mode step-down switching regulatorsprovide500mA,500mAand800mAeachand
FROM AC ADAPTER
4
WALL
FROM USB
+ -
40 VBUS
75mV (RISING) 25mV (FALLING)
BAT
Figure 1. Simplified PowerPath Block Diagram
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+ -
+ - + -
ENABLE VOUT USB CURRENT LIMIT IDEAL DIODE CONSTANT-CURRENT CONSTANT-VOLTAGE BATTERY CHARGER
4.3V (RISING) 3.2V (FALLING)
ACPR
41
VOUT
39 SYSTEM LOAD OPTIONAL EXTERNAL IDEAL DIODE PMOS
+ -
15mV
IDGATE
37
BAT
38
+
36773 F01
Li-Ion
LTC3677-3 operaTion
support100%dutycycleoperationaswellasoperating inBurstModeoperationforhighefficiencyatlightload. Noexternalcompensationcomponentsarerequiredfor theswitchingregulators.Thetwolowdropoutregulators canoutputupto150mA. Allregulatorscanbeprogrammedforaminimumoutput voltageof0.8Vandcanbeusedtopoweramicrocontrollercore,microcontrollerI/O,memoryorotherlogic circuitry. USB PowerPath Controller Theinputcurrentlimitandchargecontrolcircuitsofthe LTC3677-3isdesignedtolimitinputcurrentaswellas control battery charge current as a function of IVOUT. VOUT drives the combination of the external load, the threestep-downswitchingregulators,twoLDOsandthe batterycharger. Ifthecombinedloaddoesnotexceedtheprogrammed inputcurrentlimit,VOUTwillbeconnectedtoVBUSthrough aninternal200mP-channelMOSFET.Ifthecombined loadatVOUTexceedstheprogrammedinputcurrentlimit, thebatterychargerwillreduceitschargecurrentbythe amountnecessarytoenabletheexternalloadtobesatisfied whilemaintainingtheprogrammedinputcurrent.Evenif thebatterychargecurrentissettoexceedtheallowable USBcurrent,theaverageinputcurrentUSBspecification will not be violated. Furthermore, load current at VOUT willalwaysbeprioritizedandonlyexcessavailablecurrentwillbeusedtochargethebattery.Thecurrentout oftheCLPROGpinisafraction(1/hCLPROG)oftheVBUS current.Whenaprogrammingresistorisconnectedfrom CLPROGtoGND,thevoltageonCLPROGrepresentsthe inputcurrent: IVBUS = IBUSQ + VCLPROG *h RCLPROG CLPROG TheinputcurrentlimitisprogrammedbytheILIM0and ILIM1pins.TheLTC3677-3canbeconfiguredtolimitinput currenttooneofseveralpossiblesettingsaswellasbe deactivated(USBsuspend).Theinputcurrentlimitwillbe setbytheappropriateservovoltageandtheresistoron CLPROGaccordingtothefollowingexpression: IVBUS = IBUSQ + IVBUS = IBUSQ + IVBUS = IBUSQ + 0.2V RCLPROG 1V RCLPROG 2V RCLPROG * hCLPROG 1x Mode
( ( (
) ) )
* hCLPROG 5x Mode
* hCLPROG 10 x Mode
Underworst-caseconditions,theUSBspecificationfor averageinputcurrentwillnotbeviolatedwithanRCLPROG resistor of 2.1k or greater. Table 1 shows the available settingsfortheILIM0andILIM1pins:
Table 1. Controlled Input Current Limit
ILIM1 1 1 0 0 ILIM0 1 0 1 0 IBUS(LIM) 100mA(1x) 1A(10x) Suspend 500mA(5x)
NoticethatwhenILIM0islowandILIM1ishigh,theinput currentlimitissettoahighercurrentlimitforincreased chargingandcurrentavailabilityatVOUT.Thismodeis typically used when there is a higher power, non-USB sourceavailableattheVBUSpin.
where IBUSQ and hCLPROG are given in the Electrical Characteristicstable.
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0
LTC3677-3 operaTion
Ideal Diode from BAT to VOUT TheLTC3677-3hasaninternalidealdiodeaswellasa controllerforanoptionalexternalidealdiode.Boththe internal and the external ideal diodes respond quickly whenever VOUT drops below BAT. If the load increases beyondtheinputcurrentlimit,additionalcurrentwillbe pulledfromthebatteryviatheidealdiodes.Furthermore,if powertoVBUS(USB)orVOUT(externalwallpowerorhigh voltageregulator)isremoved,thenalloftheapplication powerwillbeprovidedbythebatteryviatheidealdiodes. TheidealdiodesarefastenoughtokeepVOUTfromdroppingsignificantlybelowVBATwithjusttherecommended outputcapacitor(seeFigure2).Theidealdiodeconsists ofaprecisionamplifierthatenablesanon-chipP-channel MOSFETwheneverthevoltageatVOUTisapproximately 15mV(VFWD)belowthevoltageatBAT.Theresistanceof theinternalidealdiodeisapproximately200m.Ifthisis sufficientfortheapplication,thennoexternalcomponents arenecessary.However,iflowerresistanceisneeded,an externalP-channelMOSFETcanbeaddedfromBATto VOUT.TheIDGATEpinoftheLTC3677-3drivesthegateof theexternalP-channelMOSFETforautomaticidealdiode control.ThesourceoftheMOSFETshouldbeconnectedto VOUTandthedrainshouldbeconnectedtoBAT.Capableof drivinga1nFload,theIDGATEpincancontrolanexternal P-channelMOSFEThavingextremelylowon-resistance. Using the WALL Pin to Detect the Presence of an External Power Source TheWALLinputpincanbeusedtoidentifythepresence ofanexternalpowersource(particularlyonethatisnot subjecttoafixedcurrentlimitliketheUSBVBUSinput). Typically,suchapowersupplywouldbea5Vwalladapter outputorthelowvoltageoutputofahighvoltagebuck regulator.Whenthewalladapteroutput(orbuckregulator output)isconnecteddirectlytotheWALLpin,andthevoltageexceedstheWALLpinthreshold,theUSBpowerpath (fromVBUStoVOUT)willbedisconnected.Furthermore, theACPRpinwillbepulledlow.Inorderforthepresence ofanexternalpowersupplytobeacknowledged,bothof thefollowingconditionsmustbesatisfied: 1.The WALL pin voltage must exceed approximately 4.3V. 2.TheWALLpinvoltagemustbegreaterthan75mVabove theBATpinvoltage. The input power path (between VBUS and VOUT) is re- enabledandtheACPRpinispulledhighwheneitherof thefollowingconditionsismet: 1.TheWALLpinvoltagefallstowithin25mVoftheBAT pinvoltage. 2.TheWALLpinvoltagefallsbelow3.2V. Each of these thresholds is suitably filtered in time to preventtransientglitchesontheWALLpinfromfalsely triggeringanevent. Suspend Mode
CHARGE DISCHARGE
4.0V VOUT 3.8V 3.6V 500mA IBAT 0
-500mA IVOUT LOAD 1A 0A
VBAT = 3.8V VBUS = 5V 5x MODE COUT = 10F
10s/DIV
36773 F02
When ILIM0 is pulled high and ILIM1 is pulled low the LTC3677-3 enters suspend mode to comply with the USBspecification.Inthismode,thepowerpathbetween VBUSandVOUTisputinahighimpedancestatetoreduce theVBUSinputcurrentto50A.Ifnootherpowersource is available to drive WALL and VOUT, the system load connectedtoVOUTissuppliedthroughtheidealdiodes connectedtoBAT.
Figure 2. Ideal Diode Transient Response
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LTC3677-3 operaTion
VBUS Undervoltage Lockout (UVLO) and Undervoltage Current Limit (UVCL) An internal undervoltage lockout circuit monitors VBUS andkeepstheinputcurrentlimitcircuitryoffuntilVBUS risesabovetherisingUVLOthreshold(3.8V)andatleast 50mVaboveVOUT.HysteresisontheUVLOturnsoffthe inputcurrentlimitifVBUSdropsbelow3.7Vor50mVbelow VOUT.Whenthishappens,systempoweratVOUTwillbe drawnfromthebatteryviatheidealdiode.Tominimizethe possibilityofoscillationinandoutofUVLOwhenusing resistiveinputsupplies,theinputcurrentlimitisreduced asVBUSfallsbelow4.45V(typ). Battery Charger The LTC3677-3 includes a constant-current/constant- voltagebatterychargerwithautomaticrecharge,automatic terminationbysafetytimer,lowvoltagetricklecharging, badcelldetectionandthermistorsensorinputforoutof temperaturechargepausing.Whenabatterychargecycle begins,thebatterychargerfirstdeterminesifthebattery isdeeplydischarged.IfthebatteryvoltageisbelowVTRKL, typically2.85V,anautomatictricklechargefeaturesetsthe batterychargecurrentto10%oftheprogrammedvalue.If thelowvoltagepersistsformorethan1/2hour,thebattery chargerautomaticallyterminates.Oncethebatteryvoltage isabove2.85V,thebatterychargerbeginscharginginfull powerconstant-currentmode.Thecurrentdeliveredto thebatterywilltrytoreach1000V/RPROG.Dependingon availableinputpowerandexternalloadconditions,the batterychargermayormaynotbeabletochargeatthe full programmed rate. The external load will always be prioritizedoverthebatterychargecurrent.TheUSBcurrentlimitprogrammingwillalwaysbeobservedandonly additionalcurrentwillbeavailabletochargethebattery. Whensystemloadsarelight,batterychargecurrentwill bemaximized. Charge Termination The battery charger has a built-in safety timer. When the battery voltage approaches the float voltage, the charge current begins to decrease as the LTC3677-3 entersconstant-voltagemode.Oncethebatterycharger detectsthatithasenteredconstant-voltagemode,the fourhoursafetytimerisstarted.Afterthesafetytimer expires, charging of the battery will terminate and no morecurrentwillbedelivered. Automatic Recharge After the battery charger terminates, it will remain off drawingonlymicroamperesofcurrentfromthebattery. Iftheportableproductremainsinthisstatelongenough, thebatterywilleventuallyselfdischarge.Toensurethat thebatteryisalwaystoppedoff,achargecyclewillautomatically begin when the battery voltage falls below VRECHRG (typically 4.1V for LTC3677-3). In the event thatthesafetytimerisrunningwhenthebatteryvoltage fallsbelowVRECHRG,thetimerwillresetbacktozero.To preventbriefexcursionsbelowVRECHRGfromresetting thesafetytimer,thebatteryvoltagemustbebelowVRECHRG formorethan1.3ms.Thechargecycleandsafetytimer willalsorestartiftheVBUSUVLOcycleslowandthenhigh (e.g.,VBUS,isremovedandthenreplaced). Charge Current Thechargecurrentisprogrammedusingasingleresistor fromPROGtoground.1/1000thofthebatterychargecurrentisdeliveredtoPROGwhichwillattempttoservoto 1.000V.Thus,thebatterychargecurrentwilltrytoreach 1000 times the current in the PROG pin. The program resistorandthechargecurrentarecalculatedusingthe followingequations: RPROG = 1000 V 1000 V ,ICHG = ICHG RPROG
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Ineithertheconstant-currentorconstant-voltagecharging modes,thePROGpinvoltagewillbeproportionaltothe actualchargecurrentdeliveredtothebattery.Therefore, theactualchargecurrentcanbedeterminedatanytime bymonitoringthePROGpinvoltageandusingthefollowingequation: IBAT = VPROG * 1000 RPROG charger.EventhoughchargingisstoppedduringanNTC faulttheCHRGpinwillstaylowindicatingthatcharging isnotcomplete. Battery Charger Stability Considerations TheLTC3677-3'sbatterychargercontainsbothaconstantvoltageandaconstant-currentcontrolloop.Theconstantvoltageloopisstablewithoutanycompensationwhena batteryisconnectedwithlowimpedanceleads.Excessive leadlength,however,mayaddenoughseriesinductance torequireabypasscapacitorofatleast1FfromBATto GND.Furthermore,a4.7Fcapacitorinserieswitha0.2 to1resistorfromBATtoGNDisrequiredtokeepripple voltagelowwhenthebatteryisdisconnected. Highvalue,lowESRmultilayerceramicchipcapacitors reducetheconstant-voltageloopphasemargin,possibly resultingininstability.Ceramiccapacitorsupto22Fmay beusedinparallelwithabattery,butlargerceramicsshould bedecoupledwith0.2to1ofseriesresistance. Inconstant-currentmode,thePROGpinisinthefeedbackloopratherthanthebatteryvoltage.Becauseofthe additional pole created by any PROG pin capacitance, capacitanceonthispinmustbekepttoaminimum.With noadditionalcapacitanceonthePROGpin,thebattery charger is stable with program resistor values as high as 25k. However, additional capacitance on this node reducesthemaximumallowedprogramresistor.Thepole frequencyatthePROGpinshouldbekeptabove100kHz. Therefore,ifthePROGpinhasaparasiticcapacitance, CPROG,thefollowingequationshouldbeusedtocalculate themaximumresistancevalueforRPROG: RPROG 1 2 * 100kHz * CPROG
Inmanycases,theactualbatterychargecurrent,IBAT,will belowerthanICHGduetolimitedinputcurrentavailableand prioritizationwiththesystemloaddrawnfromVOUT. Thermal Regulation TopreventthermaldamagetotheICorsurroundingcomponents,aninternalthermalfeedbackloopwillautomatically decreasetheprogrammedchargecurrentifthedietemperaturerisestoapproximately110C.Thermalregulation protectstheLTC3677-3fromexcessivetemperaturedueto highpoweroperationorhighambientthermalconditions andallowstheusertopushthelimitsofthepowerhandling capabilitywithagivencircuitboarddesignwithoutrisk ofdamagingtheLTC3677-3orexternalcomponents.The benefitoftheLTC3677-3thermalregulationloopisthat chargecurrentcanbesetaccordingtoactualconditions ratherthanworst-caseconditionswiththeassurancethat thebatterychargerwillautomaticallyreducethecurrent inworst-caseconditions. Charge Status Indication TheCHRGpinindicatesthestatusofthebatterycharger. Anopen-drainoutput,theCHRGpincandriveanindicator LED through a current limiting resistor for human interfacingorsimplyapull-upresistorformicroprocessorinterfacing.Whenchargingbegins,CHRGispulled lowandremainslowforthedurationofanormalcharge cycle.Whenchargingiscomplete,i.e.,thechargerentersconstant-voltagemodeandthechargecurrenthas droppedtoone-tenthoftheprogrammedvalue,theCHRG pinisreleased(highimpedance).TheCHRGpindoesnot respondtotheC/10thresholdiftheLTC3677-3isininput currentlimit.Thispreventsfalseend-of-chargeindicationsduetoinsufficientpoweravailabletothebattery
NTC Thermistor and Battery Voltage Reduction Thebatterytemperatureismeasuredbyplacinganegative temperature coefficient (NTC) thermistor close to the battery pack. To use this feature connect the NTC thermistor,RNTC,betweentheNTCpinandgroundanda biasresistor,RNOM,fromNTCBIAStoNTC.RNOMshould bea1%resistorwithavalueequaltothevalueofthe chosenNTCthermistorat25C(R25).TheLTC3677-3will
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pausechargingwhentheresistanceoftheNTCthermistor dropsto0.54timesthevalueofR25orapproximately 54k(foraVishaycurve1thermistor,thiscorrespondsto approximately40C).Ifthebatterychargerisinconstantvoltage(float)mode,thesafetytimeralsopausesuntilthe thermistorindicatesareturntoavalidtemperature.Asthe temperaturedrops,theresistanceoftheNTCthermistor rises.TheLTC3677-3isalsodesignedtopausecharging whenthevalueoftheNTCthermistorincreasesto3.25 timesthevalueofR25.ForaVishaycurve1thermistor thisresistance,325k,correspondstoapproximately0C. Thehotandcoldcomparatorseachhaveapproximately 3Cofhysteresistopreventoscillationaboutthetrippoint. ThetypicalNTCcircuitisshowninFigure3. Toimprovesafetyandreliabilitythebatteryvoltageisreducedwhenthebatterytemperaturebecomesexcessively high.WhentheresistanceoftheNTCthermistordrops toabout0.35timesthevalueofR25orapproximately 35k(foraVishaycurve1thermistor,thiscorrespondsto approximately50C)theNTCenablescircuitrytomonitorthebatteryvoltage.Ifthebatteryvoltageisabovethe batterydischargethreshold(about3.9V)thenthebattery dischargecircuitryisenabledanddrawsabout140mAfrom thebatterywhenVBUS=0Vandabout180mAwhenVBUS =5V.Thebatterydischargecurrentisdisabledbelowthe batterydischargethreshold.
NTCBIAS 34 RNOM 100k NTC 35 RNTC 100k 0.35 * NTCBIAS 0.76 * NTCBIAS
Whenthechargerisdisabledaninternalwatchdogtimer samplestheNTCthermistorforabout150severy150ms andwillenablethebatterymonitoringcircuitryifthebatterytemperatureexceedstheNTCTOO_HOTthreshold. IfaddingacapacitortotheNTCpinforfilteringthetime constantmustbemuchlessthan150ssothattheNTC pincansettletoitsfinalvalueduringthesamplingperiod. Atimeconstantlessthan10sisrecommended.Once thebatterymonitoringcircuitryisenableditwillremain enabledandmonitoringthebatteryvoltageuntilthebattery temperaturefallsbackbelowthedischargetemperature threshold.Thebatterydischargecircuitryisonlyenabled ifthebatteryvoltageisgreaterthanthebatterydischarge threshold. Alternate NTC Thermistors and Biasing TheLTC3677-3providestemperaturequalifiedchargingif agroundedthermistorandabiasresistorareconnected toNTC.Byusingabiasresistorwhosevalueisequalto theroomtemperatureresistanceofthethermistor(R25) theupperandlowertemperaturesarepre-programmed toapproximately40Cand0C,respectively(assuming aVishaycurve1thermistor). Theupperandlowertemperaturethresholdscanbeadjustedbyeitheramodificationofthebiasresistorvalue
NTC BLOCK
LTC3677-3
-
TOO_COLD
+ -
TOO_HOT
+ + -
BATTERY OVERTEMP
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0.26 * NTCBIAS
Figure 3. Typical NTC Thermistor Circuit
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orbyaddingasecondadjustmentresistortothecircuit. Ifonlythebiasresistorisadjusted,theneithertheupper orthelowerthresholdcanbemodifiedbutnotboth.The othertrippointwillbedeterminedbythecharacteristics ofthethermistor.Usingthebiasresistorinadditiontoan adjustmentresistor,boththeupperandthelowertemperaturetrippointscanbeindependentlyprogrammedwith theconstraintthatthedifferencebetweentheupperand lowertemperaturethresholdscannotdecrease.Examples ofeachtechniquearegivenbelow. NTCthermistorshavetemperaturecharacteristicswhich areindicatedonresistance-temperatureconversiontables. TheVishay-DalethermistorNTHS0603N011-N1003F ,used inthefollowingexamples,hasanominalvalueof100k and follows the Vishay curve 1 resistance-temperature characteristic. Intheexplanationbelow,thefollowingnotationisused. R25=Valueofthethermistorat25C RNTC|COLD=Valueofthermistoratthecoldtrippoint RNTC|HOT=Valueofthethermistoratthehottrippoint rCOLD=RatioofRNTC|COLDtoR25 rHOT=RatioofRNTC|HOTtoR25 RNOM=Primarythermistorbiasresistor(seeFigure3) R1=Optionaltemperaturerangeadjustmentresistor (seeFigure4) ThetrippointsfortheLTC3677-3'stemperaturequalificationareinternallyprogrammedat0.35*VNTCforthehot thresholdand0.76*VNTCforthecoldthreshold. Therefore,thehottrippointissetwhen: RNTC|HOT RNOM + RNTC|HOT * NTCBIAS = 0.35 * NTCBIAS SolvingtheseequationsforRNTC|COLDandRNTC|HOTresults inthefollowing: RNTC|HOT=0.538*RNOM and RNTC|COLD=3.17*RNOM BysettingRNOMequaltoR25,theaboveequationsresult inrHOT=0.538andrCOLD=3.17.Referencingtheseratios totheVishayresistance-temperaturecurve1chartgivesa hottrippointofabout40Candacoldtrippointofabout 0C.Thedifferencebetweenthehotandcoldtrippoints isapproximately40C. By using a bias resistor, RNOM, different in value from R25,thehotandcoldtrippointscanbemovedineither direction.Thetemperaturespanwillchangesomewhatdue tothenonlinearbehaviorofthethermistor.Thefollowing equationscanbeusedtoeasilycalculateanewvaluefor thebiasresistor: r RNOM = HOT * R25 0.538 rCOLD * R25 3.17 where rHOT and rCOLD are the resistance ratios at the desiredhotandcoldtrippoints.Notethattheseequations RNOM =
NTCBIAS 34 RNOM 105k NTC 35 R1 12.7k RNTC 100k 0.76 * NTCBIAS NTC BLOCK LTC3677-3
-
TOO_COLD
+ -
0.35 * NTCBIAS TOO_HOT
+ + -
BATTERY OVERTEMP
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andthecoldtrippointissetwhen: RNTC|COLD RNOM + RNTC|COLD * NTCBIAS = 0.76 * NTCBIAS
0.26 * NTCBIAS
Figure 4. NTC Thermistor Circuit with Additional Bias Resistor
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arelinked.Therefore,onlyoneofthetwotrippointscan bechosen,theotherisdeterminedbythedefaultratios designedintheIC. Consideranexamplewherea60Chottrippointisdesired. FromtheVishaycurve1R-Tcharacteristics,rHOTis0.2488 at60C.Usingtheaboveequation,RNOMshouldbeset to46.4k.WiththisvalueofRNOM,thecoldtrippointis about16C.Noticethatthespanisnow44Cratherthan theprevious40C.Thisisduetothedecreaseintemperaturegainofthethermistorasabsolutetemperature increases. Theupperandlowertemperaturetrippointscanbeindependentlyprogrammedbyusinganadditionalbiasresistor asshowninFigure4.Thefollowingformulascanbeused tocomputethevaluesofRNOMandR1: r -r RNOM = COLD HOT * R25 2.714 R1 = 0.536 * RNOM - rHOT * R25 Forexample,tosetthetrippointsto0Cand45Cwith aVishaycurve1thermistorchoose: RNOM = 3.266 - 0.4368 * 100k = 104.2k 2.714 Overvoltage Protection (OVP) The LTC3677-3 can protect itself from the inadvertent application of excessive voltage to VBUS or WALL with justtwoexternalcomponents:anN-channelMOSFETand a6.2kresistor.Themaximumsafeovervoltagemagnitude willbedeterminedbythechoiceoftheexternalN-channel MOSFETanditsassociateddrainbreakdownvoltage. Theovervoltageprotectionmoduleconsistsoftwopins. Thefirst,OVSENS,isusedtomeasuretheexternallyapplied voltagethroughanexternalresistor.Thesecond,OVGATE, isanoutputusedtodrivethegatepinofanexternalFET. ThevoltageatOVSENSwillbelowerthantheOVPinput voltage by (IOVSENS * 6.2k) due to the OVP circuit's quiescentcurrent.TheOVPinputwillbe200mVto400mV higherthanOVSENSundernormaloperatingconditions. WhenOVSENSisbelow6V,aninternalchargepumpwill drive OVGATE to approximately 1.88 * OVSENS. This willenhancetheN-channelMOSFETandprovidealow impedance connection to VBUS or WALL which will, in turn,powertheLTC3677-3.IfOVSENSshouldriseabove 6V(6.35VOVPinput)duetoafaultoruseofanincorrect walladapter,OVGATEwillbepulledtoGND,disablingthe externalFETtoprotectdownstreamcircuitry.Whenthe voltagedropsbelow6Vagain,theexternalFETwillbe re-enabled. In an overvoltage condition, the OVSENS pin will be clamped at 6V. The external 6.2k resistor must be sized appropriately to dissipate the resultant power. Forexample,a1/10W6.2kresistorcanhaveatmost PMAX*6.2k=24Vappliedacrossitsterminals.Withthe 6VatOVSENS,themaximumovervoltagemagnitudethat thisresistorcanwithstandis30V.A1/4W6.2kresistor raisesthisvalueto45V. ThechargepumpoutputonOVGATEhaslimitedoutput drivecapability.Caremustbetakentoavoidleakageon thispin,asitmayadverselyaffectoperation.
thenearest1%valueis105k. R1=0.536*105k-0.4368*100k=12.6k thenearest1%valueis12.7k.Thefinalsolutionisshown inFigure4andresultsinanuppertrippointof45Cand alowertrippointof0C.
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Dual Input Overvoltage Protection ItispossibletoprotectbothVBUSandWALLfromovervoltagedamagewithseveraladditionalcomponents,as showninFigure5.SchottkydiodesD1andD2passthe largerofV1andV2toR1andOVSENS.IfeitherV1orV2 exceeds6VplusVF(SCHOTTKY),OVGATEwillbepulledto GNDandboththeWALLandUSBinputswillbeprotected. Eachinputisprotecteduptothedrain-sourcebreakdown, BVDSS,ofMN1andMN2.R1mustalsoberatedforthe powerdissipatedduringmaximumovervoltage.Seethe OvervoltageProtectionsectionforanexplanationofthis calculation.Table2showssomeN-channelMOSFETsthat maybesuitableforovervoltageprotection.
Table 2. Recommended Overvoltage FETs
N-CHANNEL MOSFET Si1472DH Si2302ADS Si2306BDS Si2316BDS IRLML2502 BVDSS 30V 20V 30V 30V 20V RON 82m 60m 65m 80m 35m PACKAGE SC70-6 SOT-23 SOT-23 SOT-23 SOT-23
Reverse Input Voltage Protection TheLTC3677-3canalsobeeasilyprotectedagainstthe applicationofreversevoltageasshowninFigure6.D1 andR1arenecessarytolimitthemaximumVGSseenby MP1duringpositiveovervoltageevents.D1'sbreakdown voltage must be safely below MP1's BVGS. The circuit showninFigure6offersforwardvoltageprotectionup to MN1's BVDSS and reverse voltage protection up to MP1'sBVDSS.
USB/WALL ADAPTER MP1 D1 R1 500k MN1 C1 VBUS LTC3677-3
R2 6.2k
OVGATE OVSENS
D1: 5.6V ZENER MP1: Si2323 DS, BVDSS = 20V VBUS POSITIVE PROTECTION UP TO BVDSS OF MN1 VBUS NEGATIVE PROTECTION UP TO BVDSS OF MP1
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Figure 6. Dual Polarity Voltage Protection
V1
MN1
WALL LTC3677-3 OVGATE
LOW DROPOUT LINEAR REGULATOR OPERATION LDO Operation and Voltage Programming The LTC3677-3 contains two 150mA adjustable output LDOregulators.ThefirstLDO(LDO1)isalwaysonand will be enabled whenever VOUT is greater than VOUT UVLO. The second LDO (LDO2) is controlled by the pushbuttonandisthefirstsupplytosequenceupinresponsetopushbuttonapplication.BothLDOsaredisabled whenVOUTislessthanVOUTUVLOandLDO2isfurther disabled when the pushbutton circuity is in the power downorpoweroffstates.BothLDOscontainasoft-start functiontolimitinrushcurrentwhenenabled.Thesoft-start functionworksbyrampinguptheLDOreferenceovera 200speriod(typical)whentheLDOisenabled. WhendisabledallLDOcircuitryispoweredoffleaving onlyafewnanoampsofleakagecurrentontheLDOsupply.BothLDOoutputsareindividuallypulledtoground throughinternalresistorswhendisabled.
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V2 D2
D1 MN2 R1
C1
VBUS
OVSENS
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Figure 5. Dual Input Overvoltage Protection
LTC3677-3 operaTion
ThepowergoodstatusbitsofLDO1andLDO2areavailableinI2Cthroughtheread-backregistersPGLDO[1]and PGLDO[2]forLDO1andLDO2respectively.Thepower goodcomparatorsforbothLDOsaresampledwhenthe I2CportreceivesthecorrectI2Creadaddress. Figure7showstheLDOapplicationcircuit.Thefull-scale outputvoltageforeachLDOisprogrammedusingaresistor dividerfromtheLDOoutput(LDO1orLDO2)connected tothefeedbackpins(LDO1_FBorLDO2_FB)suchthat: R1 VLDOx = 0.8 V * +1 R2 Forstability,eachLDOoutputmustbebypassedtoground withaminimum1Fceramiccapacitor(COUT).
VINLDOx LDOxEN 0 1
MP
LDOx LDOx_FB 0.8V R1 COUT
LDOx OUTPUT
step-downswitchingregulatorsalsoincludesoft-startto limitinrushcurrentwhenpoweringon,short-circuitcurrentprotection,andswitchnodeslewlimitingcircuitryto reduceEMIradiation.Noexternalcompensationcomponentsarerequiredfortheswitchingregulators.Switching regulators1and2(Buck1andBuck2)aresequencedup anddowntogetherthroughthepushbuttoninterface(see thePushbuttonInterfacesectionformoreinformation), whileBuck3hasanindividualenablepin(EN3)thatisactivewhenthepushbuttonisinthepower-uporpower-on states.Buck3isdisabledinthepowerdownandpoweroff states.Itisrecommendedthatthestep-downswitching regulatorinputsupplies(VIN12andVIN3)beconnectedtothe systemsupplypin(VOUT).Thisisrecommendedbecause theundervoltagelockoutcircuitontheVOUTpin(VOUT UVLO)disablesthestep-downswitchingregulatorswhen theVOUTvoltagedropsbelowtheVOUTUVLOthreshold.If drivingthestep-downswitchingregulatorinputsupplies from a voltage other than VOUT the regulators should notbeoperatedoutsidethespecifiedoperatingrangeas operationisnotguaranteedbeyondthisrange. Output Voltage Programming Figure8 shows the step-down switching regulator application circuit. The full-scale output voltage for each step-down switching regulator is programmed using a resistordividerfromthestep-downswitchingregulator output connected to the feedback pins (FB1, FB2 and FB3)suchthat: R1 VOUTx = 0.8 V * +1 R2
VIN EN MODE PWM SLEW CONTROL
GND
R2
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Figure 7. LDO Application Circuit
STEP-DOWN SWITCHING REGULATOR OPERATION Introduction TheLTC3677-3includesthree2.25MHzconstant-frequency currentmodestep-downswitchingregulatorsproviding 500mA,500mAand800mAeach.Allstep-downswitchingregulatorscanbeprogrammedforaminimumoutput voltageof0.8Vandcanbeusedtopoweramicrocontroller core,microcontrollerI/O,memoryorotherlogiccircuitry. Allstep-downswitchingregulatorssupport100%duty cycleoperation(lowdropoutmode)whentheinputvoltagedropsveryclosetotheoutputvoltageandarealso capableofBurstModeoperationforhighestefficiencies atlightloads.BurstModeoperationisindividuallyselectableforeachstep-downswitchingregulatorthroughthe I2CregisterbitsBK1BRST,BK2BRSTandBK3BRST.The
MP MN
SWx
L CFB R1
VOUTx COUT
FBx 0.8V GND R2
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Figure 8. Step-Down Switching Regulator Application Circuit
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TypicalvaluesforR1areintherangeof40kto1M.The capacitorCFBcancelsthepolecreatedbyfeedbackresistorsandtheinputcapacitanceoftheFBpinandalsohelps toimprovetransientresponseforoutputvoltagesmuch greaterthan0.8V.Avarietyofcapacitorsizescanbeused forCFBbutavalueof10pFisrecommendedformostapplications.Experimentationwithcapacitorsizesbetween 2pFand22pFmayyieldimprovedtransientresponse. Operating Modes Thestep-downswitchingregulatorsincludetwopossible operatingmodestomeetthenoise/powerneedsofavariety ofapplications.Inpulse-skippingmode,aninternallatch issetatthestartofeverycycle,whichturnsonthemain P-channelMOSFETswitch.Duringeachcycle,acurrent comparator compares the peak inductor current to the output of an error amplifier. The output of the current comparatorresetstheinternallatch,whichcausesthemain P-channelMOSFETswitchtoturnoffandtheN-channel MOSFETsynchronousrectifiertoturnon.TheN-channel MOSFETsynchronousrectifierturnsoffattheendofthe 2.25MHz cycle or if the current through the N-channel MOSFETsynchronousrectifierdropstozero.Usingthis methodofoperation,theerroramplifieradjuststhepeak inductorcurrenttodelivertherequiredoutputpower.All necessary compensation is internal to the step-down switchingregulatorrequiringonlyasingleceramicoutput capacitorforstability.Atlightloadsinpulse-skippingmode, theinductorcurrentmayreachzerooneachpulsewhich willturnofftheN-channelMOSFETsynchronousrectifier. Inthiscase,theswitchnode(SW1,SW2orSW3)goes highimpedanceandtheswitchnodevoltagewillring.This isdiscontinuousoperation,andisnormalbehaviorfora switchingregulator.Atverylightloadsinpulse-skipping mode,thestep-downswitchingregulatorswillautomaticallyskippulsesasneededtomaintainoutputregulation. Athighdutycycle(VOUTXapproachingVINX)itispossible fortheinductorcurrenttoreverseatlightloadscausing thesteppeddownswitchingregulatortooperatecontinuously.Whenoperatingcontinuously,regulationandlow noiseoutputvoltagearemaintained,butinputoperating currentwillincreasetoafewmilliamps. In Burst Mode operation, the step-down switching regulatorsautomaticallyswitchbetweenfixedfrequency PWMoperationandhystereticcontrolasafunctionof theloadcurrent.Atlightloadsthestep-downswitchingregulatorscontroltheinductorcurrentdirectlyand use a hysteretic control loop to minimize both noise andswitchinglosses.WhileoperatinginBurstMode operation,theoutputcapacitorischargedtoavoltage slightlyhigherthantheregulationpoint.Thestep-down switchingregulatorthengoesintosleepmode,during whichtheoutputcapacitorprovidestheloadcurrent.In sleepmode,mostoftheswitchingregulator'scircuitry is powered down, helping conserve battery power. Whentheoutputvoltagedropsbelowapre-determined value, the step-down switching regulator circuitry is poweredonandanotherburstcyclebegins.Thesleep timedecreasesastheloadcurrentincreases.Beyond a certain load current point (about 1/4 rated output loadcurrent)thestep-downswitchingregulatorswill switchtoalownoiseconstant-frequencyPWMmode ofoperation,muchthesameaspulse-skippingoperationathighloads. For applications that can tolerate some output ripple atlowoutputcurrents,BurstModeoperationprovides betterefficiencythanpulse-skippingatlightloads.The step-down switching regulators allow mode transition on-the-fly,providingseamlesstransitionbetweenmodes evenunderload.Thisallowstheusertoswitchbackand forthbetweenmodestoreduceoutputrippleorincrease lowcurrentefficiencyasneeded.BurstModeoperation is individually selectable for each step-down switching regulatorthroughtheI2CregisterbitsBK1BRST,BK2BRST andBK3BRST. Shutdown Thestep-downswitchingregulators(Buck1,Buck2and Buck3)areshutdownwhenthepushbuttoncircuitryisin thepower-downorpower-offstate.Step-downswitching regulator3(Buck3)canalsobeshutdownbybringingthe EN3inputlow.Inshutdownallcircuitryinthestep-down switchingregulatorisdisconnectedfromtheswitching regulatorinputsupplyleavingonlyafewnanoampsof leakagecurrent.Thestep-downswitchingregulatoroutputsareindividuallypulledtogroundthroughinternal10k resistorsontheswitchpin(SW1,SW2orSW3)whenin shutdown.
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Dropout Operation Itispossibleforastep-downswitchingregulator'sinput voltagetoapproachitsprogrammedoutputvoltage(e.g., abatteryvoltageof3.4Vwithaprogrammedoutputvoltageof3.3V).Whenthishappens,theP-ChannelMOSFET switchdutycycleincreasesuntilitisturnedoncontinuouslyat100%.Inthisdropoutcondition,therespective outputvoltageequalstheregulator'sinputvoltageminus thevoltagedropsacrosstheinternalP-channelMOSFET andtheinductor. Soft-Start Operation Soft-startisaccomplishedbygraduallyincreasingthepeak inductorcurrentforeachstep-downswitchingregulator overa500speriod.Thisallowseachoutputtoriseslowly, helpingminimizeinrushcurrentrequiredtochargeupthe switching regulator output capacitor. A soft-start cycle occurswheneveragivenswitchingregulatorisenabled. Asoft-startcycleisnottriggeredbychangingoperating modes. This allows seamless output transition when activelychangingbetweenoperatingmodes.
100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 0.01 0.1 1 10 IOUT3 (A) Burst Mode OPERATION VIN = 3.8V SW[1:0] = 00 01 10 11 100 10 100 POWER LOSS (mW) EFFICIENCY (%) 1000
Slew Rate Control The step-down switching regulators contain patented circuitrytolimittheslewrateoftheswitchnode(SW1, SW2andSW3).Thisnewcircuitryisdesignedtotransitiontheswitchnodeoveraperiodofafewnanoseconds, significantlyreducingradiatedEMIandconductedsupply noisewhilemaintaininghighefficiency.Sinceslowingthe slewrateoftheswitchnodescausesefficiencyloss,the slewrateofthestep-downswitchingregulatorsisadjustableviatheI2CregistersSLEWCTL1andSLEWCTL2.This allowstheusertooptimizeefficiencyorEMIasnecessary withfourdifferentslewratesettings.Thepowerupdefault isthefastestslewrate(highestefficiency)setting.Figures 9and10showtheefficiencyandpowerlossgraphfor Buck3programmedfor1.2Vand2.5Voutputs.Notethat the power loss curves remain fairly constant for both graphsyetchangingtheslewratehasalargereffecton the1.2Voutputefficiency.Thisismainlybecausefora givenoutputcurrentthe2.5Voutputisdeliveringmore than2xthepowerthanthe1.2Voutput.Efficiencywill alwaysdecreaseandshowmorevariationtoslewrateas theprogrammedoutputvoltageisdecreased.
100 90 80 70 60 50 40 30 20 10 0 0.01 0.1 10 1 IOUT3 (A) Burst Mode OPERATION VIN = 3.8V SW[1:0] = 00 01 10 11 100 10 100 POWER LOSS (mW) 1000
1
1
0.1
0.1
0.001 1000
0.01 1000
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Figure 9. VOUT3 (1.2V) Efficiency and Power Loss vs IOUT3
Figure 10. VOUT3 (2.5V) Efficiency and Power Loss vs IOUT3
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Low Supply Operation An undervoltage lockout circuit on VOUT (VOUT UVLO) shutsdownthestep-downswitchingregulatorswhenVOUT dropsbelowabout2.7V.Itisrecommendedthatthestepdownswitchingregulatorinputsupplies(VIN12,VIN3)be connectedtothepowerpathoutput(VOUT)directly.This UVLOpreventsthestep-downswitchingregulatorsfrom operatingatlowsupplyvoltageswherelossofregulationorotherundesirableoperationmayoccur.Ifdriving the step-down switching regulator input supplies from avoltageotherthantheVOUTpin,theregulatorsshould notbeoperatedoutsidethespecifiedoperatingrangeas operationisnotguaranteedbeyondthisrange. Inductor Selection Manydifferentsizesandshapesofinductorsareavailable fromnumerousmanufacturers.Choosingtherightinductor fromsuchalargeselectionofdevicescanbeoverwhelming, butfollowingafewbasicguidelineswillmaketheselection processmuchsimpler.Thestep-downswitchingregulatorsaredesignedtoworkwithinductorsintherangeof 2.2Hto10H.Formostapplicationsa4.7Hinductoris suggestedforstep-downswitchingregulatorsproviding upto500mAofoutputcurrentwhilea3.3Hinductoris suggestedforstep-downswitchingregulatorsproviding upto800mA.Largervalueinductorsreduceripplecurrent, whichimprovesoutputripplevoltage.Lowervalueinductorsresultinhigherripplecurrentandimprovedtransient responsetime,butwillreducetheavailableoutputcurrent. Tomaximizeefficiency,chooseaninductorwithalowDC resistance.Fora1.2Voutput,efficiencyisreducedabout 2%for100mseriesresistanceat400mAloadcurrent, andabout2%for300mseriesresistanceat100mAload current.ChooseaninductorwithaDCcurrentratingat least1.5timeslargerthanthemaximumloadcurrentto ensurethattheinductordoesnotsaturateduringnormal operation.Ifoutputshortcircuitisapossiblecondition, theinductorshouldberatedtohandlethemaximumpeak currentspecifiedforthestep-downconverters.Different core materials and shapes will change the size/current and price/current relationship of an inductor. Toroid or shieldedpotcoresinferriteorPermalloymaterialsare smallanddonotradiatemuchenergy,butgenerallycost more than powdered iron core inductors with similar electricalcharacteristics.Inductorsthatareverythinor haveaverysmallvolumetypicallyhavemuchhighercore andDCRlosses,andwillnotgivethebestefficiency.The
Table 3. Recommended Inductors for Step-Down Switching Regulators
INDUCTOR TYPE DB318C D312C DE2812C CDRH3D16 CDRH2D11 CLS4D09 SD3118 SD3112 SD12 SD10 LPS3015 *TypicalDCR L (H) 4.7 3.3 4.7 3.3 4.7 3.3 4.7 3.3 4.7 3.3 4.7 4.7 3.3 4.7 3.3 4.7 3.3 4.7 3.3 4.7 3.3 MAX IDC (A) 1.07 1.20 0.79 0.90 1.15 1.37 0.9 1.1 0.5 0.6 0.75 1.3 1.59 0.8 0.97 1.29 1.42 1.08 1.31 1.1 1.3 MAX DCR () 0.1 0.07 0.24 0.20 0.13* 0.105* 0.11 0.085 0.17 0.123 0.19 0.162 0.113 0.246 0.165 0.117* 0.104* 0.153* 0.108* 0.2 0.13 SIZE in mm (L x W x H) 3.8x3.8x1.8 3.8x3.8x1.8 3.6x3.6x1.2 3.6x3.6x1.2 3.0x2.8x1.2 3.0x2.8x1.2 4x4x1.8 4x4x1.8 3.2x3.2x1.2 3.2x3.2x1.2 4.9x4.9x1 3.1x3.1x1.8 3.1x3.1x1.8 3.1x3.1x1.2 3.1x3.1x1.2 5.2x5.2x1.2 5.2x5.2x1.2 5.2x5.2x1.0 5.2x5.2x1.0 3.0x3.0x1.5 3.0x3.0x1.5 MANUFACTURER Toko www.toko.com
Sumida www.sumida.com
Cooper www.cooperet.com
CoilCraft www.coilcraft.com
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choiceofwhichstyleinductortouseoftendependsmore onthepriceversussize,performance,andanyradiated EMIrequirementsthanonwhatthestep-downswitching regulatorsrequirestooperate.Theinductorvaluealsohas aneffectonBurstModeoperation.Lowerinductorvalues willcauseBurstModeswitchingfrequencytoincrease. Table3showsseveralinductorsthatworkwellwiththe step-downswitchingregulators.Theseinductorsoffera good compromise in current rating, DCR and physical size.Consulteachmanufacturerfordetailedinformation ontheirentireselectionofinductors. Input/Output Capacitor Selection LowESR(equivalentseriesresistance)ceramiccapacitors should be used at both step-down switching regulator outputsaswellasateachstep-downswitchingregulator inputsupply.OnlyX5RorX7Rceramiccapacitorsshould beusedbecausetheyretaintheircapacitanceoverwider voltageandtemperaturerangesthanotherceramictypes. A10Foutputcapacitorissufficientforthestep-down switchingregulatoroutputs.Forgoodtransientresponse andstabilitytheoutputcapacitorforstep-downswitching regulatorsshouldretainatleast4Fofcapacitanceover operatingtemperatureandbiasvoltage.Eachswitching regulatorinputsupplyshouldbebypassedwitha2.2F capacitor.Consultwithcapacitormanufacturersfordetailed information on their selection and specifications of ceramic capacitors. Many manufacturers now offer verythin(<1mmtall)ceramiccapacitorsidealforusein height-restricteddesigns.Table4showsalistofseveral ceramiccapacitormanufacturers.
Table 4. Ceramic Capacitor Manufacturers
AVX Murata TaiyoYuden VishaySiliconix TDK www.avxcorp.com www.murata.com www.t-yuden.com www.vishay.com www.tdk.com
I2C OPERATION I2C Interface TheLTC3677-3maycommunicatewithabusmasterusingthestandardI2C2-wireinterface.Thetimingdiagram inFigure11showstherelationshipofthesignalsonthe bus. The two bus lines, SDA and SCL, must be HIGH whenthebusisnotinuse.Externalpull-upresistorsor currentsources,suchastheLTC1694SMBusaccelerator, arerequiredontheselines.TheLTC3677-3isbothaslave receiver and slave transmitter. The I2C control signals, SDAandSCLarescaledinternallytotheDVCCsupply. DVCCshouldbeconnectedtothesamepowersupplyas thebuspull-upresistors. TheI2CporthasanundervoltagelockoutontheDVCCpin. WhenDVCCisbelowapproximately1V,theI2Cserialport isclearedandregistersaresettothedefaultconfigurationofallzeros. I2C Bus Speed TheI2Cportisdesignedtobeoperatedatspeedsofup to400kHz.Ithasbuilt-intimingdelaystoensurecorrect operationwhenaddressedfromanI2Ccompliantmaster device.Italsocontainsinputfiltersdesignedtosuppress glitchesshouldthebusbecomecorrupted. I2C START and STOP Conditions Abusmastersignalsthebeginningofcommunicationsby transmittingaSTARTcondition.ASTARTconditionisgeneratedbytransitioningSDAfromHIGHtoLOWwhileSCLis HIGH.Themastermaytransmiteithertheslavewriteorthe slavereadaddress.OncedataiswrittentotheLTC3677-3, themastermaytransmitaSTOPconditionwhichcommandstheLTC3677-3toactuponitsnewcommandset.A STOPconditionissentbythemasterbytransitioningSDA fromLOWtoHIGHwhileSCLisHIGH.Thebusisthenfree forcommunicationwithanotherI2Cdevice. I2C Byte Format EachbytesenttoorreceivedfromtheLTC3677-3must be 8 bits long followed by an extra clock cycle for the acknowledgebit.ThedatashouldbesenttotheLTC3677-3 mostsignificantbit(MSB)first.
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ADDRESS 0 0 0 1 0 0 1 WR 0 A7 A6 A5 DATA BYTE A A4 A3 A2 A1 A0 B7 B6 B5 DATA BYTE B B4 B3 B2 B1 B0
START SDA 0 0 0 1 0 0 1 0 ACK ACK ACK
STOP
SCL
1
2
3
4
5
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7
8
9
1
2
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4
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7
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9
1
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8
9
SDA tSU, DAT tSU, STA tBUF tSU, STO
tLOW SCL tHD, STA START CONDITION tr
tHD, DAT
tHD, STA
tHIGH tf REPEATED START CONDITION
tSP STOP CONDITION START CONDITION
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Figure 11. I2C Timing Diagram
I2C Acknowledge Theacknowledgesignalisusedforhandshakingbetween themasterandtheslave.WhentheLTC3677-3iswritten to(writeaddress),itacknowledgesitswriteaddressas wellasthesubsequenttwodatabytes.Whenreadfrom (readaddress),theLTC3677-3acknowledgesitsreadaddressonly.Thebusmastershouldacknowledgereceipt ofinformationfromtheLTC3677-3. Anacknowledge(activeLOW)generatedbytheLTC3677-3 letsthemasterknowthatthelatestbyteofinformationwas received.Theacknowledgerelatedclockpulseisgenerated bythemaster.ThemasterreleasestheSDAline(HIGH) duringtheacknowledgeclockcycle.TheLTC3677-3pulls downtheSDAlineduringthewriteacknowledgeclock pulsesothatitisastableLOWduringtheHIGHperiod ofthisclockpulse. WhentheLTC3677-3isreadfrom,itreleasestheSDAline sothatthemastermayacknowledgereceiptofthedata. SincetheLTC3677-3onlytransmitsonebyteofdata,a masternotacknowledgingthedatasentbytheLTC3677-3 hasnoI2Cspecificconsequenceontheoperationofthe I2Cport.
I2C Slave Address The LTC3677-3 responds to a 7-bit address which has beenfactoryprogrammedtob'0001001[R/W]'.TheLSB oftheaddressbyte,knownastheread/writebit,shouldbe 0whenwritingdatatotheLTC3677-3and1whenreading datafromit.Consideringtheaddressan8-bitword,then thewriteaddressis0x12andthereadaddressis0x13. TheLTC3677-3willacknowledgebothitsreadandwrite address. I2C Sub-Addressed Writing The LTC3677-3 has one command register for control input.ItisaccessedbytheI2Cportviaasub-addressed writingsystem. Each write cycle of the LTC3677-3 consists of exactly threebytes.ThefirstbyteisalwaystheLTC3677-3'swrite address. The second byte represents the LTC3677-3's sub-address.Thesub-addressisapointerwhichdirects thesubsequentdatabytewithintheLTC3677-3.Thethird byte consists of the data to be written to the location pointedtobythesub-address.TheLTC3677-3contains controlregistersatonlysub-addresslocation0x00.Subaddressesoutside0x00shouldnotbewrittentoasthey accessfunctionalitynotavailableintheLTC3677-3.
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I2C Bus Write Operation ThemasterinitiatescommunicationwiththeLTC3677-3 withaSTARTconditionandtheLTC3677-3'swriteaddress. IftheaddressmatchesthatoftheLTC3677-3,theLTC3677-3 returnsanacknowledge.Themastershouldthendeliver thesub-address.AgaintheLTC3677-3acknowledgesand thecycleisrepeatedforthedatabyte.Thedatabyteis transferredtoaninternalholdinglatchuponthereturnof itsacknowledgebytheLTC3677-3.Thisproceduremustbe repeatedforeachsub-addressthatrequiresnewdata.After oneormorecyclesof[ADDRESS][SUB-ADDRESS][DATA], themastermayterminatethecommunicationwithaSTOP condition.Alternatively,aREPEAT-STARTconditioncan beinitiatedbythemasterandanotherchipontheI2Cbus can be addressed. This cycle can continue indefinitely andtheLTC3677-3willrememberthelastinputofvalid datathatitreceived.Onceallchipsonthebushavebeen addressedandsentvaliddata,aglobalSTOPcanbesent andtheLTC3677-3willupdateitscommandlatcheswith thedatathatitreceived. I2C Bus Read Operation ThebusmasterreadsthestatusoftheLTC3677-3with aSTARTconditionfollowedbytheLTC3677-3readaddress.IfthereadaddressmatchesthatoftheLTC3677-3, the LTC3677-3 returns an acknowledge. Following the acknowledgementoftheirreadaddress,theLTC3677-3 returnsonebitofstatusinformationforeachofthenext 8clockcycles.ASTOPcommandisnotrequiredforthe busreadoperation. I2C Input Data Thereisonebyteofdatathatcanbewrittentoonthe LTC3677-3.Thebyteisaccessedthroughthesub-address 0x00. At first power application (VBUS, WALL or BAT) allbitsdefaultto0.Additionally,allbitsareclearedto0 whenDVCCdropsbelowitsundervoltagelockoutorifthe pushbuttonentersthepowerdown(PDN)state. Table5showsthebyteofdatathatcanbewrittentoat sub-address0x00.Thisbyteofdataisreferredtoasthe buckcontrolregister.
Table 5. Buck Control Register
BUCK CONTROL REGISTER BIT B0 B1 B2 B3 B4 B5 B6 B7 NAME N/A N/A BK1BRST BK2BRST BK3BRST SLEWCTL1 SLEWCTL2 N/A ADDRESS:00010010 SUB-ADDRESS:00000000 FUNCTION NotUsed--NoEffectOnOperation NotUsed--NoEffectOnOperation Buck1BurstModeEnable Buck2BurstModeEnable Buck2BurstModeEnable BuckSWSlewRate:00=1ns, 01=2ns,10=4ns,11=8ns NotUsed--NoEffectOnOperation
BitsB2,B3,andB4settheoperatingmodesofthestepdownswitchingregulators(bucks).Writinga1toanyof thesethreeregisterswillputthatrespectivebuckconverter inthehighefficiencyBurstModeoperation,whilea0will enablethelownoisepulse-skippingmodeofoperation. TheB5andB6bitsadjusttheslewrateofallSWpins togethersotheyallslewatthesamerate.Itisrecommendedthatthefastestslewrate(B6:B5=00)beused unlessEMIisanissueintheapplicationasslowerslew ratescausereducedefficiency. I2C Output Data One status byte may be read from the LTC3677-3, as showninTable6.A1readbackintheanyofthebitposi-
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tionsindicatesthattheconditionistrue.Forexample,1 readbackfrombitA3indicatethatLDO1isenabledand regulating correctly. A status read from the LTC3677-3 captures the status information when the LTC3677-3 acknowledgeitsreadaddress.
Table 6. I2C READ Register
STATUS REGISTER BIT A0 A1 A2 A3 A4 A5 A6 A7 NAME CHARGE STAT[0] STAT[1] PGLDO[1] PGLDO[2] PGBCK[1] PGBCK[2] PGBCK[3] ADDRESS:00010011 SUB-ADDRESS:None FUNCTION ChargeStatus(1=Charging) STAT[1:0];00=NoFault 01=TOOCOLD/HOT 10=BATTERYOVERTEMP 11=BATTERYFAULT LDO1PowerGood LDO2PowerGood Buck1PowerGood Buck2PowerGood Buck3PowerGood
catesthateitherLDO2isnotenabled,orthattheLDO2is enabled,butisoutofregulationbymorethan8%. BitA3showsthepowergoodstatusofLDO1.A1indicates thatLDO1isenabledandisregulatingcorrectly.A0indicatesthateitherLDO1isnotenabled,orthattheLDO1is enabled,butisoutofregulationbymorethan8%. Bits A2 and A1 indicate the fault status of the charger measurementcircuitandaredecodedinTable6.Thetoo cold/hotstateindicatesthatthethermistortemperatureis outofthevalidchargingrange(eitherbelow0Corabove 40Cforacurve1thermistor)andthatcharginghaspaused untilthebatteryreturnstovalidchargingtemperature.The batteryovertemperaturestateindicatesthatthebattery's thermistor has reached a critical temperature (about 50Cforacurve1thermistor)andthatlong-termbattery capacitymaybeseriouslycompromisedifthecondition persists.Thebatteryfaultstateindicatesthatanattempt wasmadetochargealowbattery(typically<2.85V)but thatthelowvoltageconditionpersistedformorethan1/2 hour.Inthiscasecharginghasterminated. Bit A0 indicates the status of the battery charger. A 1 indicatesthatthechargerisenabledandisintheconstant-current charge state. In this case the battery is beingchargedunlesstheNTCthermistorisoutsideits validchargerangeinwhichcasechargingistemporarily suspendedbutnotcomplete.Chargingwillcontinueonce thebatteryhasreturnedtoavalidchargingtemperature. A0inbitA0indicatesthatchargerhasreachedend-ofcharge(hC/10)andisnearVFLOATorthatcharginghasbeen terminated.Chargingcanbeterminatedbyreachingthe endofthechargetimerorbyabatteryfaultasdescribed previously.
BitA7showsthepowergoodstatusofBuck3.A1indicates thatBuck3isenabledandisregulatingcorrectly.A0indicatesthateitherBuck3isnotenabled,orthattheBuck3is enabled,butisoutofregulationbymorethan8%. BitA6showsthepowergoodstatusofBuck2.A1indicates thatBuck2isenabledandisregulatingcorrectly.A0indicatesthateitherBuck2isnotenabled,orthattheBuck2is enabled,butisoutofregulationbymorethan8%. BitA5showsthepowergoodstatusofBuck1.A1indicates thatBuck1isenabledandisregulatingcorrectly.A0indicatesthateitherBuck1isnotenabled,orthattheBuck1is enabled,butisoutofregulationbymorethan8%. BitA4showsthepowergoodstatusofLDO2.A1indicates thatLDO2isenabledandisregulatingcorrectly.A0indi-
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PUSHBUTTON INTERFACE OPERATION State Diagram/Operation Figure13showstheLTC3677-3pushbuttonstatediagram. Uponfirstapplicationofpower(VBUS,WALLorBAT)an internalpower-onreset(POR)signalplacesthepushbuttoncircuitryintothepower-off(POFF)state.Thefollowing eventscausethestatemachinetotransitionoutofPOFF intothepower-up(PUP)state: 1)ONinputLOWfor50ms(PB50MS) 2)PWR_ONinputgoingHIGH(PWR_ON) Upon entering the PUP state, the pushbutton circuitry willsequenceupLDO2,Buck1andBuck2inthatorder. OnesecondafterenteringthePUPstate,thepushbutton circuitrywilltransitionintothepower-on(PON)state.Note that the PWR_ON input must be brought HIGH before enteringthePONstateifthepartistoremaininthePON state.Buck3canbeenabledthroughtheEN3inputonce thepushbuttonisinthePUPorPONstates. PWR_ONgoingLOW,orVOUTdroppingtoitsundervoltage lockout(VOUTUVLO)thresholdwillcausethestatemachine toleavethePONstateandenterthepower-down(PDN) state.ThePDNstateresetstheI2Cregistersaswellas disablesBuck1,Buck2andLDO2together.Buck3isalso disabledinthePDNandPOFFstates.Theoneseconddelay beforeleavingthepower-downstateallowsthesuppliesto powerdowncompletelybeforetheycanbere-enabled.
PB50ms + PWR_ON POR POFF PUP 1SEC
PBSTAT Operation PBSTATgoesLOW50msaftertheinitialpushbuttonapplication(ONLOW)andwillstaylowfor50msminimum. PBSTATwillgoHIGHcoincidentwithONgoingHIGHunless ONgoesHIGHbeforethe50msminimumLOWtime. Hard Reset and PGOOD Operation Thehardreseteventisgeneratedbypressingandholding thepushbutton(ONinputLOW)for14seconds.Fora validhardreseteventtooccurtheinitialpushbuttonapplicationmuststartinthePUPorPONstate.Thisavoids causingahardresetfromoccurringiftheuserhangson the pushbutton during initial power-up. If a valid hard reseteventispresentthenthePGOODoutputwilltransitionLOWforabout1.8mstoallowthemicroprocessorto reset.Thehardreseteventdoesnotaffecttheoperating stateorregulatoroperation. ThePGOODpinisanopen-drainoutputusedtoindicate thatBuck1,Buck2andLDO1areenabledandhavereached theirfinalregulationvoltage.A230msdelayisincluded fromthetimeBuck1,Buck2andLDO1reach92%oftheir regulationvaluetoallowasystemcontrollerampletimeto resetitself.PGOODisanopen-drainoutputandrequiresa pull-upresistortoanappropriatepowersource.Optimally thepull-upresistorisconnectedtotheoutputofBuck1, Buck2orLDO2sothatpowerisnotdissipatedwhilethe regulatorsaredisabled. Pushbutton Operation and VOUT UVLO As stated earlier VOUT dropping to its UVLO threshold willcausethepushbuttontoleavethepower-onstateand enterthepower-downstate,thuspoweringdownBuck1, Buck2,Buck3andLDO2.Additionally,LDO1isdisabled wheninUVLO.Thus,allLTC3677-3suppliesaredisabled andremaindisabledaslongastheVOUTUVLOcondition exists.ItisnotpossibletopowerupanyoftheLTC3677-3 generatedsupplieswhileVOUTisbelowtheVOUTUVLO threshold.
PON UVLO + PWR_ON PDN
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1SEC
Figure 12. Pushbutton State Diagram
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Power-Up via Pushbutton Timing The timing diagram, Figure 13, shows the LTC3677-3 poweringupthroughapplicationoftheexternalpushbutton.Forthisexamplethepushbuttoncircuitrystartsin thePOFFstatewithVOUTnotinUVLOandBuck1,Buck2 andLDO2disabled.Pushbuttonapplication(ONLOW)for 50mstransitionsthepushbuttoncircuitryintothePUP statewhichsequencesupLDO2,Buck1andBuck2inthat order.PWR_ONmustbedrivenHIGHbeforethe1second PUPperiodisovertokeepsuppliesup.IfPWR_ONis LOWorgoesLOWafterthe1secondPUPperiodBuck1, Buck2,andLDO2willbeshutdowntogether.PGOODis assertedonceBuck1,Buck2andLDO1arewithin8%of theirregulationvoltagefor230ms. Buck3canbeenabledanddisabledatanytimeviaEN3 onceinthePUPorPONstates.ThePWR_ONinputcan bedrivenviaaP/Corbyoneofthesequencedoutputs through a high impedance (100k typ). PBSTAT goes LOW 50ms after the initial pushbutton application and willstayLOWfor50msminimum.PBSTATwillgoHIGH coincident with ON going HIGH unless ON goes HIGH beforethe50msminimumLOWtime.
VOUT UVLO ON (PB) 50ms PBSTAT LDO2 BUCK1 BUCK2 PGOOD PWR_ON STATE POFF PUP PON
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Power-Up via PWR_ON Timing The timing diagram, Figure 14, shows the LTC3677-3 poweringupbydrivingPWR_ONHIGH.Forthisexample thepushbuttoncircuitrystartsinthePOFFstatewithVOUT notinUVLOandBuck1,Buck2andLDO2disabled.50ms afterPWR_ONgoesHIGHthepushbuttoncircuitrytransitionsintothePUPstatewhichsequencesupLDO2,Buck1 andBuck2inthatorder.PWR_ONmustbedrivenhigh beforethe1secondPUPperiodisovertokeepsupplies up.IfPWR_ONisLOWorgoesLOWafterthe1second PUPperiodBuck1,Buck2andLDO2willbeshutdown together.PGOODisassertedonceBuck1,Buck2andLD01 arewithin8%oftheirregulationvoltagefor230ms. Buck3canbeenabledanddisabledatanytimeviaEN3 onceinthePUPorPONstates. Powering up via PWR_ON is useful for applications containinganalwaysonmicrocontroller.Thisallowsthe microcontroller to power the application up and down forhousekeepingandotheractivitiesoutsidetheuser's control.
VOUT UVLO ON (PB) PBSTAT 1 SEC 14ms PWR_ON LDO2 230ms 1 SEC BUCK1 BUCK2 230ms PGOOD STATE POFF PUP
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50ms 14ms
PON
Figure 13. Power-Up via Pushbutton
Figure 14. Power-Up via PWR_ON
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Power Down via Pushbutton Timing The timing diagram, Figure 15, shows the LTC3677-3 poweringdownbyC/Pcontrol.Forthisexamplethe pushbutton circuitry starts in the PON state with VOUT not in UVLO and Buck1, Buck2 and LDO2 enabled. In thiscasethepushbuttonisapplied(ONLOW)foratleast 50ms,whichgeneratesalowimpedanceonthePBSTAT output.AfterreceivingthePBSTATtheC/Pwilldrive thePWR_ONinputLOW.50msafterPWR_ONgoesLOW thepushbuttoncircuitrywillenterthePDNstate.Buck1, Buck2andLDO2aredisabledtogetheruponenteringthe PDNstate.AfterenteringthePDNstate,a1secondwait timeisinitiatedbeforeenteringthePOFFstate.During this1secondtimeONandPWR_ONinputsareignored toallowallLTC3677-3generatedsuppliestogoLOW. UponenteringthePDNstateBuck3isdisabledandthe I2Cregistersarecleared.HoldingONLOWthroughthe 1secondpower-downperiodwillnotcauseapower-up eventatendofthe1secondperiod.TheONinputmustbe broughtHIGHfollowingthepower-downeventandthen goLOWagaintoestablishavalidpower-upevent. VOUT UVLO Power-Down Timing IfVOUTdropsbelowtheVOUTUVLOthreshold,thepushbuttoncircuitrywilltransitionfromthePONstatetothe PDNstate.Buck1,Buck2andLDO2aredisabledtogether uponenteringthePDNstate.AfterenteringthePDNstate, a1secondwaittimeisinitiatedbeforeenteringthePOFF state.Duringthis1secondtimeONandPWR_ONinputs areignoredtoallowallLTC3677-3generatedsuppliesto goLOW. UponenteringthePDNstatetheBuck3isdisabledand theI2Cregistersarecleared.LDO1isalsodisabledby theVOUTUVLOandstaysdisabledaslongastheVOUT UVLOconditionremains.Notethatitisnotpossibleto sequenceanyofthesuppliesupwhiletheVOUTUVLO condition exists. LDO1 will be re-enabled when the VOUT UVLO condition is removed. The other supplies willremaindisableduntilavalidpower-uppushbutton eventtakesplace.
VOUT UVLO ON (PB) 50ms PBSTAT PWR_ON BUCK1 BUCK2 LDO2 PGOOD STATE PON PDN 50ms C/P CONTROL
VOUT UVLO 1 SEC ON (PB) LDO1 PBSTAT PWR_ON BUCK1 BUCK2 LDO2 POFF
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1 SEC
PGOOD STATE PON PDN POFF
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Figure 15. Power-Down via Pushbutton
Figure 16. VOUT UVLO Power-Down
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Hard Reset Timing HardresetprovidesawaytoresettheC/Pincaseofa softwarelockup.Toinitiateahardreset,thepushbuttonis pressed(ONLOW)andheldforgreaterthan14seconds. OncethehardresettimeisexceededthePGOODinput willgoLOWfor1.8mswhichresetstheC/P .Operation oftheenabledsuppliesisnoteffectedbythehardreset event.Allenabledsuppliesshouldremaininregulation and operating correctly assuming specified operating conditionsaremet(i.e.,noshortedsupplies,etc). ThereareonlytwomethodstopowerdowntheLTC3677-3 supplies:1)PWR_ONgoesLOW;2)VOUTdropsbelowthe VOUTUVLOthreshold.IftheC/Pcontrolsshutdownby bringingPWR_ONLOW,itispossiblethattheapplication canhangwithallsuppliesenablediftheC/Pfailsto resetcorrectlyonhardreset.Inthiscasethebatterywill continuetobedraineduntilVOUTdropsbelowtheVOUT UVLOthreshold,ortheuserintervenestoshutdownthe applicationmanually.Theapplicationcanbeshutdown manuallybyremovingthebatteryandanyexternalsupplies, orbyprovidingasuicidebuttonthatwillbringPWR_ON LOWwhenpressed.
VOUT UVLO ON (PB) PBSTAT PWR_ON BUCK1 BUCK2 LDO1 14 SEC PGOOD STATE PON 1.8ms
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Power-Up Sequencing Figure18showstheactualpower-upsequencingofthe LTC3677-3.Buck1,Buck2andLDO2areallinitiallydisabled (0V).Oncethepushbuttonhasbeenapplied(ONLOW) for50msPBSTATgoesLOWandLDO2isenabled.Once enabled,LDO2slewsupandentersregulation.Theactual slewrateiscontrolledbythesoft-startfunctionofLDO2 whichrampstheLDOreferenceupovera200speriod typically.Aftera14msdelayfromLDO2beingenabled, Buck1isenabledandslewsupintoregulation.WhenBuck1 iswithinabout8%offinalregulation,Buck2isenabled andslewsupintoregulation.Thebucksalsohaveasoftstartfunctiontolimitinrushcurrentatstart-up.230ms afterBuck2iswithin8%offinalregulation,thePGOOD outputwillgohighimpedance(notshowninFigure18). TheregulatorsinFigure18areslewingupwithnominal outputcapacitorsandnoload.Addingaloadorincreasing outputcapacitanceonanyoftheoutputswillreducethe slewrateandlengthenthetimeittakestheregulatorto getintoregulation.
>14 SEC 50ms
1 PBSTAT 0 LDO2 1V/DIV 0V BUCK1 1V/DIV 0V BUCK2 2V/DIV 0V
2ms/DIV
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Figure 18. Power-Up Sequencing
Figure 17. Hard Reset Timing
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LTC3677-3 operaTion
LAYOUT AND THERMAL CONSIDERATIONS Printed Circuit Board Power Dissipation Inordertobeabletodelivermaximumchargecurrent underallconditions,itiscriticalthattheexposedground padonthebacksideoftheLTC3677-3packagebesolderedtoagroundplaneontheboard.Correctlysoldered to2500mm2groundplaneonadouble-sided1ozcopper boardtheLTC3677-3hasathermalresistance(JA)ofapproximately45C/W.Failuretomakegoodthermalcontact betweentheexposedpadonthebacksideofthepackage andaadequatelysizedgroundplanewillresultinthermal resistancesfargreaterthan45C/W. TheconditionsthatcausetheLTC3677-3toreducecharge currentduetothethermalprotectionfeedbackcanbeapproximatedbyconsideringthepowerdissipatedinthepart. ForhighchargecurrentswithawalladapterappliedtoVOUT, theLTC3677-3powerdissipationisapproximately: PD=(VOUT-BAT)*IBAT+PDREGS wherePDisthetotalpowerdissipated,VOUTisthesupply voltage,BATisthebatteryvoltageandIBATisthebattery chargecurrent.PDREGSisthesumofpowerdissipatedonchipbythestep-downswitching,andLDOregulators. Thepowerdissipatedbyastep-downswitchingregulator canbeestimatedasfollows: PD(SWx ) = OUTx * IOUTx whereLDOxistheprogrammedoutputvoltage,VINLDOx istheLDOsupplyvoltageandILDOxistheLDOoutput loadcurrent.NotethatiftheLDOsupplyisconnectedto oneofthebuckoutput,thenitssupplycurrentmustbe addedtothebuckregulatorloadcurrentforcalculating thebuckpowerloss. Thusthepowerdissipatedbyallregulatorsis: PDREGS=PDSW1+PDSW2+PDSW3+PDLDO1+PDLDO2 Itisnotnecessarytoperformanyworst-casepowerdissipationscenariosbecausetheLTC3677-3willautomatically reducethechargecurrenttomaintainthedietemperature atapproximately110C.However,theapproximateambienttemperatureatwhichthethermalfeedbackbeginsto protecttheICis: TA=110C-PD*JA Example:ConsidertheLTC3677-3operatingfromawall adapterwith5V(VOUT)providing1A(IBAT)tochargea Li-Ionbatteryat3.3V(BAT).AlsoassumePDREGS=0.3W, sothetotalpowerdissipationis: PD=(5V-3.3V)*1A+0.3W=2W TheambienttemperatureabovewhichtheLTC3677-3beginstoreducethe1Achargecurrent,isapproximately TA=110C-2W*45C/W=20C TheLTC3677-3canbeusedabove20C,butthecharge currentwillbereducedbelow1A.Thechargecurrentata givenambienttemperaturecanbeapproximatedby: PD = 110C - TA = VOUT - BAT * IBAT + PD(REGS) JA
(
)
100 - Eff * 100
where OUTx is the programmed output voltage, IOUTx istheloadcurrentandEffisthe%efficiencywhichcan bemeasuredorlookeduponanefficiencytableforthe programmedoutputvoltage. ThepowerdissipatedonchipbyaLDOregulatorcanbe estimatedasfollows: PDLDOx=(VINLDOx-LDOx)*ILDOx
(
)
Thus:
JA - PD(REGS) I = BAT VOUT - BAT
(110C - TA )
36773f
0
LTC3677-3 operaTion
Consider the previous example with an ambient temperatureof55C.Thechargecurrentwillbereducedto approximately: 110C - 55C - 0.3W 45C/W IBAT = 5V - 3.3V IBAT = 1.22 - 0.3W = 542mA 1.7 V ConnectVIN12andVIN3toVOUTthroughashortlow impedancetrace. 3.TheswitchingpowertracesconnectingSW1,SW2, andSW3totheirrespectiveinductorsshouldbeminimizedtoreduceradiatedEMIandparasiticcoupling. Duetothelargevoltageswingoftheswitchingnodes, sensitive nodes such as the feedback nodes (FBx andLDOx_FB)shouldbekeptfarawayorshielded fromtheswitchingnodesorpoorperformancecould result. 4.Connectionsbetweenthestep-downswitchingregulatorinductorsandtheirrespectiveoutputcapacitors shouldbekeptasshortaspossible.TheGNDsideof the output capacitors should connect directly to the thermalgroundplaneofthepart. 5.Keepthebuckfeedbackpintraces(FB1,FB2,andFB3) asshortaspossible.Minimizeanyparasiticcapacitance betweenthefeedbacktracesandanyswitchingnode (i.e.,SW1,SW2,SW3,andlogicsignals).Ifnecessary shieldthefeedbacknodeswithaGNDtrace. 6.ConnectionsbetweentheLTC3677-3powerpathpins (VBUSandVOUT)andtheirrespectivedecouplingcapacitorsshouldbekeptasshortaspossible.TheGND sideofthesecapacitorsshouldconnectdirectlytothe groundplaneofthepart.
Printed Circuit Board Layout Whenlayingouttheprintedcircuitboard,thefollowing listshouldbefollowedtoensureproperoperationofthe LTC3677-3: 1.The exposed pad of the package (Pin 45) should connectdirectlytoalargegroundplanetominimize thermalandelectricalimpedance. 2.Thestep-downswitchingregulatorinputsupplypins (VIN12andVIN3)andtheirrespectivedecouplingcapacitorsshouldbekeptasshortaspossible.TheGND sideofthesecapacitorsshouldconnectdirectlytothe ground plane of the part. These capacitors provide the AC current to the internal power MOSFETs and theirdrivers.It'simportanttominimizinginductance fromthesecapacitorstothepinsoftheLTC3677-3.
36773f
LTC3677-3 Typical applicaTion
5V WALL ADAPTER 4 13 8 OVGATE OVSENSE 41 Si2333DS VOUT SYSTEM LOAD 20F
WALL ACPR
30 VINLDO2 27 VINLDO1 39 VOUT VIN12 VIN3 32 6
10F 2.2F 2.2F 1k
USB 10F 2k
40
VBUS
LTC3677-3 36
PROG CLPROG
2.1k 43 DVCC SDA SCL C/P EXTPWR PBSTAT PWR_ON KILL EN3 RST ILIM0 ILIM1 499k 499k
10 DVCC 11 SDA 12 SCL 499k 42 EXTPWR 16 PBSTAT 14 PWR_ON
44 CHRG 37 IDGATE 38 BAT 34 100k NTCBIAS 35 NTC
Si2333DS (OPT)
+
100k NTC
BAT Li-Ion
NC
3, 9, 18 ,19, 20, 22
PUSHBUTTON
17 EN3 1 ILIM0 2 ILIM1 15 ON LDO1 LDO1_FB LDO2 LDO2_FB GND 45
SW1 FB1
33 26
4.7H 10pF 806k 649k 10F
VOUT1 1.8V 500mA
VLDO1 3.3V 150mA
28 1F 324k 1.02M 23 29 1F 464k 348k 24
SW2 FB2 SW3 FB3 PGOOD
31 25 5 7 21
4.7H 10pF 3.3H 10pF 232k 464k 10F 1.02M 324k 10F
VOUT2 3.3V 500mA VOUT3 1.2V 800mA
VLDO2 1.4V 150mA
100k
36773 TA02
36773f
LTC3677-3 package DescripTion
(ReferenceLTCDWG#05-08-1762RevO) (Reference LTC DWG # 05-08-1762 Rev O)
1.48 0.05 0.70 0.05
UFF Package Variation: UFFMA UFFMA Package 44-Lead Plastic QFN (4mm x 7mm) 44-Lead Plastic QFN (4mm 7mm)
4.50 0.05 3.10 0.05 2.40 REF
2.56 0.05 2.64 0.05
1.70 0.05 2.02 0.05 2.76 0.05 0.98 0.05
PACKAGE OUTLINE 0.20 0.05 5.60 REF 6.10 0.05 7.50 0.05 0.40 BSC
RECOMMENDED SOLDER PAD LAYOUT APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 0.75 0.05 0.00 - 0.05 2.40 REF 43 44
4.00 0.10
PIN 1 NOTCH R = 0.30 TYP OR 0.35 45 CHAMFER
0.40 0.10 1 PIN 1 TOP MARK (SEE NOTE 6) 2 2.64 0.10 2.56 0.10 7.00 0.10 5.60 REF 1.70 0.10 R = 0.10 TYP 0.74 0.10 R = 0.10 TYP 0.74 0.10
(UFF44MA) QFN REF O 1107
2.76 0.10
0.200 REF
R = 0.10 TYP
0.98 0.10
0.20 0.05 0.40 BSC
BOTTOM VIEW--EXPOSED PAD NOTE: 1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
36773f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However,noresponsibilityisassumedforitsuse.LinearTechnologyCorporationmakesnorepresentationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
LTC3677-3 Typical applicaTion
5V WALL ADAPTER Si2333DS D3 5.6V R1 500k 6.2k OPTIONAL OVERVOLTAGE/ REVERSE VOLTAGE PROTECTION USB 10F 2k 36 40 13 8 Si2306BDS 4 OVGATE OVSENSE VOUT 41 30 39 32 10F 2.2F 1k Si2333DS VOUT SYSTEM LOAD 20F
WALL ACPR VINLDO1
2.1k 43 DVCC SDA SCL C/P EXTPWR PBSTAT PWR_ON KILL EN3 RST ILIM0 ILIM1 499k 499k 10 11 12
VBUS VIN12 2.2F LTC3677-3 6 VIN3 44 CHRG 37 PROG IDGATE 38 BAT CLPROG 34 100k NTCBIAS 35 DVCC NTC SDA SCL NC 3, 9, 18 ,19, 20, 22
Si2333DS (OPT)
+
100k NTC
BAT Li-Ion
499k 42 EXTPWR 16 PBSTAT 14 PWR_ON
PUSHBUTTON
17 EN3 1 ILIM0 2 ILIM1 15 ON LDO1 LDO1_FB LDO2 LDO2_FB 45
SW1 FB1 VINLDO2 SW2 FB2 SW3 FB3
33 26 30 31 25 5 7 21
4.7H 10pF 1.02M 324k 10F
VOUT1 3.3V 500mA
VLDO1 2.5V 150mA
28 1F 470k 1.00M 23 29 1F 464k 115k 24
4.7H 10pF 3.3H 10pF 402k 649k 10F 806k 649k 10F
VOUT2 1.8V 500mA VOUT3 1.3V 800mA
VLDO2 1.0V 150mA
GND PGOOD
100k
36773 TA03
relaTeD parTs
PART NUMBER LTC3556 LTC3557/ LTC3557-1 LTC3577/ LTC3577-1 DESCRIPTION HighEfficiencyUSBPowerManagerPlusDual BuckPlusBuck-BoostDC/DCPMIC COMMENTS Two400mASynchronousBuckRegulators,One1ABuck-BoostRegulator,4mmx 5mmQFN28Package.
USBPowerManagerwithLi-Ion/Polymer LinearPowerManagerandThreeBuckRegulators,4mmx4mmQFN28Package, ChargerandTripleSynchronousBuckConverter LTC3557-1VersionHas4.1VFloatVoltage. HighlyIntegratedProtable/NavigationPMIC LinearPowerManagerandThreeBuckRegulators,10-LEDBoostRegulator,2x150mA LDOs,4mmx7mmQFN44Package,LTC3577-1VersionHas4.1VFloatVoltage.
36773f LT 0310 * PRINTED IN USA
Linear Technology Corporation
(408)432-1900 FAX: (408) 434-0507 www.linear.com
1630 McCarthy Blvd., Milpitas, CA 95035-7417
LINEAR TECHNOLOGY CORPORATION 2010

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